Merge changes I76eee5c5,Ie45ab1d8,Iddcb83d3,I4425777d,I5be2837c, ... into integration
* changes: drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64() drivers/gicv3: add debug log for maximum INTID of SPI and eSPI drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET() drivers/gicv3: fix logical issue for num_eints drivers/gicv3: fix potential GICD context override with ESPI enabled drivers/gicv3: use mpidr to probe GICR for current CPU
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commit
8c8efa8620
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -105,6 +105,16 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
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/* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
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/* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
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num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
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num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
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/*
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* The GICv3 architecture allows GICD_TYPER.ITLinesNumber to be 31, so
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* the maximum possible value for num_ints is 1024. Limit the value to
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* MAX_SPI_ID + 1 to avoid getting wrong address in GICD_OFFSET() macro.
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*/
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if (num_ints > MAX_SPI_ID + 1U) {
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num_ints = MAX_SPI_ID + 1U;
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}
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INFO("Maximum SPI INTID supported: %u\n", num_ints - 1);
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/* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
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/* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
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for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) {
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for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) {
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gicd_write_igroupr(gicd_base, i, ~0U);
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gicd_write_igroupr(gicd_base, i, ~0U);
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@ -117,7 +127,8 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
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* Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
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* Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
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*/
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*/
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num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
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num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
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TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1;
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TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
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INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1);
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for (i = MIN_ESPI_ID; i < num_eints;
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for (i = MIN_ESPI_ID; i < num_eints;
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i += (1U << IGROUPR_SHIFT)) {
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i += (1U << IGROUPR_SHIFT)) {
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@ -125,6 +136,7 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
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}
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}
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} else {
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} else {
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num_eints = 0U;
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num_eints = 0U;
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INFO("ESPI range is not implemented.\n");
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}
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}
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#endif
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#endif
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -70,7 +70,8 @@ static bool is_sgi_ppi(unsigned int id);
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for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
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for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
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int_id += (1U << REG##R_SHIFT)) { \
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int_id += (1U << REG##R_SHIFT)) { \
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gicd_write_##reg((base), int_id, \
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gicd_write_##reg((base), int_id, \
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(ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - MIN_SPI_ID))\
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(ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
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round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
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>> REG##R_SHIFT]); \
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>> REG##R_SHIFT]); \
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} \
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} \
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} while (false)
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} while (false)
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@ -79,7 +80,8 @@ static bool is_sgi_ppi(unsigned int id);
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do { \
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do { \
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for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
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for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
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int_id += (1U << REG##R_SHIFT)) { \
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int_id += (1U << REG##R_SHIFT)) { \
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(ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - MIN_SPI_ID))\
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(ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
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round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
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>> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\
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>> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\
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} \
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} \
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} while (false)
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} while (false)
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@ -755,7 +757,7 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
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* Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
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* Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
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*/
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*/
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num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
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num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
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TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1;
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TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
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} else {
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} else {
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num_eints = 0U;
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num_eints = 0U;
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}
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}
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@ -879,7 +881,7 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
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* Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
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* Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
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*/
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*/
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num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
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num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
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TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1;
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TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
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} else {
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} else {
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num_eints = 0U;
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num_eints = 0U;
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}
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}
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@ -1299,8 +1301,8 @@ unsigned int gicv3_set_pmr(unsigned int mask)
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******************************************************************************/
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******************************************************************************/
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int gicv3_rdistif_probe(const uintptr_t gicr_frame)
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int gicv3_rdistif_probe(const uintptr_t gicr_frame)
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{
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{
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u_register_t mpidr;
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u_register_t mpidr, mpidr_self;
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unsigned int proc_num, proc_self;
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unsigned int proc_num;
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uint64_t typer_val;
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uint64_t typer_val;
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uintptr_t rdistif_base;
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uintptr_t rdistif_base;
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bool gicr_frame_found = false;
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bool gicr_frame_found = false;
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@ -1314,18 +1316,18 @@ int gicv3_rdistif_probe(const uintptr_t gicr_frame)
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assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
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assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
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#endif /* !__aarch64__ */
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#endif /* !__aarch64__ */
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proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1());
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mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
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rdistif_base = gicr_frame;
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rdistif_base = gicr_frame;
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do {
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do {
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typer_val = gicr_read_typer(rdistif_base);
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typer_val = gicr_read_typer(rdistif_base);
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mpidr = mpidr_from_gicr_typer(typer_val);
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if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
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if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
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mpidr = mpidr_from_gicr_typer(typer_val);
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proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
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proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
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} else {
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} else {
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proc_num = (unsigned int)(typer_val >>
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proc_num = (unsigned int)(typer_val >>
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TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK;
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TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK;
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}
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}
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if (proc_num == proc_self) {
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if (mpidr == mpidr_self) {
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/* The base address doesn't need to be initialized on
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/* The base address doesn't need to be initialized on
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* every warm boot.
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* every warm boot.
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*/
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*/
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#define GICD_OFFSET_64(REG, id) \
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#define GICD_OFFSET_64(REG, id) \
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(((id) <= MAX_SPI_ID) ? \
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(((id) <= MAX_SPI_ID) ? \
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GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
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GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
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GICD_##REG##RE + (((uintptr_t)(id) - MIN_ESPI_ID) << 3))
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GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
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REG##R_SHIFT) << 3))
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#else /* GICv3 */
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#else /* GICv3 */
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#define GICD_OFFSET_8(REG, id) \
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#define GICD_OFFSET_8(REG, id) \
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