Merge pull request #627 from soby-mathew/sm/fvp_ccn502_sup_1
Add CCN support to FVP
This commit is contained in:
commit
8c94f82c67
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@ -496,6 +496,14 @@ map is explained in the [Firmware Design].
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for functions that wait for an arbitrary time length (udelay and mdelay).
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The default value is 0.
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* `FVP_INTERCONNECT_DRIVER`: Selects the interconnect driver to be built. The
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default interconnect driver depends on the value of `FVP_CLUSTER_COUNT` as
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explained in the options below:
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- `FVP_CCI` : The CCI driver is selected. This is the default
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if 0 < `FVP_CLUSTER_COUNT` <= 2.
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- `FVP_CCN` : The CCN driver is selected. This is the default
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if `FVP_CLUSTER_COUNT` > 2.
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### Debugging options
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To compile a debug version and make the build more verbose use
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@ -254,6 +254,7 @@ static unsigned long long ccn_master_to_rn_id_map(unsigned long long master_map)
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assert(ccn_plat_desc);
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FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, master_map) {
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assert(iface_id < ccn_plat_desc->num_masters);
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/* Convert the master ID into the node ID */
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node_id = ccn_plat_desc->master_to_rn_id_map[iface_id];
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@ -501,3 +502,15 @@ void ccn_program_sys_addrmap(unsigned int sn0_id,
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}
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}
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/*******************************************************************************
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* This function returns the part0 id from the peripheralID 0 register
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* in CCN. This id can be used to distinguish the CCN variant present in the
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* system.
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******************************************************************************/
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int ccn_get_part0_id(uintptr_t periphbase)
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{
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assert(periphbase);
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return (int)(mmio_read_64(periphbase
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+ MN_PERIPH_ID_0_1_OFFSET) & 0xFF);
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}
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@ -149,6 +149,7 @@ typedef enum rn_types {
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#define MN_DDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET
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#define MN_DDC_SET_OFFSET DOMAIN_CTRL_SET_OFFSET
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#define MN_DDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET
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#define MN_PERIPH_ID_0_1_OFFSET 0xFE0
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#define MN_ID_OFFSET REGION_ID_OFFSET
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/* HNF System Address Map register bit masks and shifts */
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@ -51,6 +51,13 @@
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#define CCN_L3_RUN_MODE_HAM 0x2 /* HNF_PM_HALF */
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#define CCN_L3_RUN_MODE_FAM 0x3 /* HNF_PM_FULL */
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/* part 0 IDs for various CCN variants */
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#define CCN_502_PART0_ID 0x30
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#define CCN_504_PART0_ID 0x26
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#define CCN_505_PART0_ID 0x27
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#define CCN_508_PART0_ID 0x28
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#define CCN_512_PART0_ID 0x29
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/*
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* The following macro takes the value returned from a read of a HN-F P-state
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* status register and returns the retention state value.
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@ -107,6 +114,7 @@ void ccn_program_sys_addrmap(unsigned int sn0_id,
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unsigned int top_addr_bit1,
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unsigned char three_sn_en);
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unsigned int ccn_get_l3_run_mode(void);
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int ccn_get_part0_id(uintptr_t periphbase);
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#endif /* __ASSEMBLY__ */
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#endif /* __CCN_H__ */
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@ -30,6 +30,7 @@
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#include <arm_config.h>
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#include <arm_def.h>
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#include <ccn.h>
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#include <debug.h>
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#include <gicv2.h>
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#include <mmio.h>
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@ -213,9 +214,17 @@ void fvp_config_setup(void)
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void fvp_interconnect_init(void)
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{
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if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
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if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) {
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#if FVP_INTERCONNECT_DRIVER == FVP_CCN
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if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
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ERROR("Unrecognized CCN variant detected. Only CCN-502"
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" is supported");
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panic();
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}
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#endif
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plat_arm_interconnect_init();
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}
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}
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void fvp_interconnect_enable(void)
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{
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@ -40,6 +40,10 @@
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#define FVP_PRIMARY_CPU 0x0
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/* Defines for the Interconnect build selection */
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#define FVP_CCI 1
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#define FVP_CCN 2
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/*******************************************************************************
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* FVP memory map related constants
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******************************************************************************/
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@ -57,16 +61,23 @@
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#define DEVICE0_BASE 0x20000000
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#define DEVICE0_SIZE 0x0c200000
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/*
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* In case of FVP models with CCN, the CCN register space overlaps into
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* the NSRAM area.
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*/
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#if FVP_INTERCONNECT_DRIVER == FVP_CCN
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#define DEVICE1_BASE 0x2e000000
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#define DEVICE1_SIZE 0x1A00000
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#else
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#define DEVICE1_BASE 0x2f000000
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#define DEVICE1_SIZE 0x200000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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#endif
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/* Devices in the second GB */
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#define DEVICE2_BASE 0x7fe00000
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#define DEVICE2_SIZE 0x00200000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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#define PCIE_EXP_BASE 0x40000000
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#define TZRNG_BASE 0x7fe60000
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@ -64,7 +64,9 @@ use_ve_mmap:
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mov_imm x16, VE_GICD_BASE
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print_gic_regs:
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arm_print_gic_regs
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#if FVP_INTERCONNECT_DRIVER == FVP_CCI
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print_cci_regs
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#endif
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.endm
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#endif /* __PLAT_MACROS_S__ */
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@ -90,6 +90,10 @@
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#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
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#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
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/* CCN related constants. Only CCN 502 is currently supported */
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#define PLAT_ARM_CCN_BASE 0x2e000000
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#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID 1
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@ -39,11 +39,22 @@ $(eval $(call add_define,FVP_USE_SP804_TIMER))
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# The FVP platform depends on this macro to build with correct GIC driver.
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$(eval $(call add_define,FVP_USE_GIC_DRIVER))
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# If FVP_CLUSTER_COUNT has been defined, pass it into the build system.
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ifdef FVP_CLUSTER_COUNT
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# Define default FVP_CLUSTER_COUNT to 2 and pass it into the build system.
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FVP_CLUSTER_COUNT := 2
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$(eval $(call add_define,FVP_CLUSTER_COUNT))
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# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2,
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# choose the CCI driver , else the CCN driver
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ifeq ($(FVP_CLUSTER_COUNT), 0)
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$(error "Incorrect cluster count specified for FVP port")
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else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2))
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FVP_INTERCONNECT_DRIVER := FVP_CCI
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else
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FVP_INTERCONNECT_DRIVER := FVP_CCN
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endif
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$(eval $(call add_define,FVP_INTERCONNECT_DRIVER))
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# Choose the GIC sources depending upon the how the FVP will be invoked
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ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3)
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FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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@ -67,8 +78,15 @@ else
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$(error "Incorrect GIC driver chosen on FVP port")
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endif
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ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI)
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FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
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plat/arm/common/arm_cci.c
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else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN)
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FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
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plat/arm/common/arm_ccn.c
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else
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$(error "Incorrect CCN driver chosen on FVP port")
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endif
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FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
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plat/arm/board/fvp/fvp_security.c \
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@ -43,6 +43,9 @@ static const ccn_desc_t arm_ccn_desc = {
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.master_to_rn_id_map = master_to_rn_id_map
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};
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CASSERT(PLAT_ARM_CLUSTER_COUNT == ARRAY_SIZE(master_to_rn_id_map),
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assert_invalid_cluster_count_for_ccn_variant);
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/******************************************************************************
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* The following functions are defined as weak to allow a platform to override
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* the way ARM CCN driver is initialised and used.
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