Build option to include AArch32 registers in cpu context
The system registers that are saved and restored in CPU context include AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ, DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an AArch64-only (i.e. on hardware that does not implement AArch32, or at least not at EL1 and higher ELs) platform leads to an exception. This patch introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to include these AArch32 systems registers in the cpu context or not. By default this build option is set to 1 to ensure compatibility. AArch64-only platforms must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to verify this. Fixes ARM-software/tf-issues#386 Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee
This commit is contained in:
Soby Mathew
parent
e141aa0357
commit
8cd16e6b5b
5
Makefile
5
Makefile
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@ -62,6 +62,9 @@ NS_TIMER_SWITCH := 0
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RESET_TO_BL31 := 0
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# Include FP registers in cpu context
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CTX_INCLUDE_FPREGS := 0
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# Build flag to include AArch32 registers in cpu context save and restore
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# during world switch. This flag must be set to 0 for AArch64-only platforms.
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CTX_INCLUDE_AARCH32_REGS := 1
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# Determine the version of ARM GIC architecture to use for interrupt management
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# in EL3. The platform port can change this value if needed.
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ARM_GIC_ARCH := 2
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@ -392,6 +395,7 @@ $(eval $(call assert_boolean,DEBUG))
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$(eval $(call assert_boolean,NS_TIMER_SWITCH))
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$(eval $(call assert_boolean,RESET_TO_BL31))
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$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS))
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$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call assert_boolean,ASM_ASSERTION))
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$(eval $(call assert_boolean,USE_COHERENT_MEM))
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$(eval $(call assert_boolean,DISABLE_PEDANTIC))
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@ -419,6 +423,7 @@ $(eval $(call add_define,SPD_${SPD}))
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$(eval $(call add_define,NS_TIMER_SWITCH))
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$(eval $(call add_define,RESET_TO_BL31))
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$(eval $(call add_define,CTX_INCLUDE_FPREGS))
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$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call add_define,ARM_GIC_ARCH))
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$(eval $(call add_define,ARM_CCI_PRODUCT_ID))
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$(eval $(call add_define,ASM_ASSERTION))
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@ -32,6 +32,7 @@
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#include <assert.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <platform.h>
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/*
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@ -66,6 +67,19 @@ void bl1_prepare_next_image(unsigned int image_id)
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image_desc_t *image_desc;
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entry_point_info_t *next_bl_ep;
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#if CTX_INCLUDE_AARCH32_REGS
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/*
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* Ensure that the build flag to save AArch32 system registers in CPU
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* context is not set for AArch64-only platforms.
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*/
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if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT)
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& ID_AA64PFR0_ELX_MASK) == 0x1) {
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ERROR("EL1 supports AArch64-only. Please set build flag "
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"CTX_INCLUDE_AARCH32_REGS = 0");
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panic();
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}
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#endif
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/* Get the image descriptor. */
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image_desc = bl1_plat_get_image_desc(image_id);
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assert(image_desc);
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@ -145,6 +145,19 @@ void bl31_prepare_next_image_entry(void)
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entry_point_info_t *next_image_info;
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uint32_t image_type;
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#if CTX_INCLUDE_AARCH32_REGS
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/*
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* Ensure that the build flag to save AArch32 system registers in CPU
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* context is not set for AArch64-only platforms.
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*/
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if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT)
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& ID_AA64PFR0_ELX_MASK) == 0x1) {
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ERROR("EL1 supports AArch64-only. Please set build flag "
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"CTX_INCLUDE_AARCH32_REGS = 0");
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panic();
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}
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#endif
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/* Determine which image to execute next */
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image_type = bl31_get_next_image_type();
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@ -57,14 +57,6 @@ func el1_sysregs_context_save
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mrs x10, elr_el1
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stp x9, x10, [x0, #CTX_SPSR_EL1]
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mrs x11, spsr_abt
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mrs x12, spsr_und
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stp x11, x12, [x0, #CTX_SPSR_ABT]
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mrs x13, spsr_irq
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mrs x14, spsr_fiq
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stp x13, x14, [x0, #CTX_SPSR_IRQ]
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mrs x15, sctlr_el1
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mrs x16, actlr_el1
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stp x15, x16, [x0, #CTX_SCTLR_EL1]
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@ -93,10 +85,6 @@ func el1_sysregs_context_save
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mrs x10, tpidrro_el0
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stp x9, x10, [x0, #CTX_TPIDR_EL0]
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mrs x11, dacr32_el2
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mrs x12, ifsr32_el2
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stp x11, x12, [x0, #CTX_DACR32_EL2]
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mrs x13, par_el1
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mrs x14, far_el1
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stp x13, x14, [x0, #CTX_PAR_EL1]
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@ -109,6 +97,24 @@ func el1_sysregs_context_save
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mrs x9, vbar_el1
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stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1]
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/* Save AArch32 system registers if the build has instructed so */
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#if CTX_INCLUDE_AARCH32_REGS
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mrs x11, spsr_abt
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mrs x12, spsr_und
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stp x11, x12, [x0, #CTX_SPSR_ABT]
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mrs x13, spsr_irq
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mrs x14, spsr_fiq
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stp x13, x14, [x0, #CTX_SPSR_IRQ]
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mrs x15, dacr32_el2
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mrs x16, ifsr32_el2
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stp x15, x16, [x0, #CTX_DACR32_EL2]
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mrs x17, fpexc32_el2
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str x17, [x0, #CTX_FP_FPEXC32_EL2]
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#endif
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/* Save NS timer registers if the build has instructed so */
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#if NS_TIMER_SWITCH
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mrs x10, cntp_ctl_el0
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@ -123,9 +129,6 @@ func el1_sysregs_context_save
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str x14, [x0, #CTX_CNTKCTL_EL1]
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#endif
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mrs x15, fpexc32_el2
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str x15, [x0, #CTX_FP_FPEXC32_EL2]
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ret
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endfunc el1_sysregs_context_save
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@ -143,14 +146,6 @@ func el1_sysregs_context_restore
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msr spsr_el1, x9
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msr elr_el1, x10
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ldp x11, x12, [x0, #CTX_SPSR_ABT]
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msr spsr_abt, x11
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msr spsr_und, x12
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ldp x13, x14, [x0, #CTX_SPSR_IRQ]
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msr spsr_irq, x13
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msr spsr_fiq, x14
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ldp x15, x16, [x0, #CTX_SCTLR_EL1]
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msr sctlr_el1, x15
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msr actlr_el1, x16
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@ -179,10 +174,6 @@ func el1_sysregs_context_restore
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msr tpidr_el0, x9
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msr tpidrro_el0, x10
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ldp x11, x12, [x0, #CTX_DACR32_EL2]
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msr dacr32_el2, x11
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msr ifsr32_el2, x12
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ldp x13, x14, [x0, #CTX_PAR_EL1]
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msr par_el1, x13
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msr far_el1, x14
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@ -195,6 +186,23 @@ func el1_sysregs_context_restore
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msr contextidr_el1, x17
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msr vbar_el1, x9
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/* Restore AArch32 system registers if the build has instructed so */
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#if CTX_INCLUDE_AARCH32_REGS
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ldp x11, x12, [x0, #CTX_SPSR_ABT]
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msr spsr_abt, x11
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msr spsr_und, x12
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ldp x13, x14, [x0, #CTX_SPSR_IRQ]
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msr spsr_irq, x13
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msr spsr_fiq, x14
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ldp x15, x16, [x0, #CTX_DACR32_EL2]
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msr dacr32_el2, x15
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msr ifsr32_el2, x16
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ldr x17, [x0, #CTX_FP_FPEXC32_EL2]
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msr fpexc32_el2, x17
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#endif
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/* Restore NS timer registers if the build has instructed so */
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#if NS_TIMER_SWITCH
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ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0]
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@ -209,11 +217,7 @@ func el1_sysregs_context_restore
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msr cntkctl_el1, x14
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#endif
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ldr x15, [x0, #CTX_FP_FPEXC32_EL2]
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msr fpexc32_el2, x15
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/* No explict ISB required here as ERET covers it */
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ret
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endfunc el1_sysregs_context_restore
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@ -380,6 +380,12 @@ performed.
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any register that is not part of the SBSA generic UART specification.
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Default value is 0 (a full PL011 compliant UART is present).
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* `CTX_INCLUDE_AARCH32_REGS` : Boolean option that, when set to 1, will cause
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the AArch32 system registers to be included when saving and restoring the
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CPU context. The option must be set to 0 for AArch64-only platforms (that
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is on hardware that does not implement AArch32, or at least not at EL1 and
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higher ELs). Default value is 1.
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* `CTX_INCLUDE_FPREGS`: Boolean option that, when set to 1, will cause the FP
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registers to be included when saving and restoring the CPU context. Default
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is 0.
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@ -91,48 +91,58 @@
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#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
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#define CTX_SPSR_EL1 0x0
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#define CTX_ELR_EL1 0x8
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#define CTX_SPSR_ABT 0x10
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#define CTX_SPSR_UND 0x18
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#define CTX_SPSR_IRQ 0x20
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#define CTX_SPSR_FIQ 0x28
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#define CTX_SCTLR_EL1 0x30
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#define CTX_ACTLR_EL1 0x38
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#define CTX_CPACR_EL1 0x40
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#define CTX_CSSELR_EL1 0x48
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#define CTX_SP_EL1 0x50
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#define CTX_ESR_EL1 0x58
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#define CTX_TTBR0_EL1 0x60
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#define CTX_TTBR1_EL1 0x68
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#define CTX_MAIR_EL1 0x70
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#define CTX_AMAIR_EL1 0x78
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#define CTX_TCR_EL1 0x80
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#define CTX_TPIDR_EL1 0x88
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#define CTX_TPIDR_EL0 0x90
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#define CTX_TPIDRRO_EL0 0x98
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#define CTX_DACR32_EL2 0xa0
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#define CTX_IFSR32_EL2 0xa8
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#define CTX_PAR_EL1 0xb0
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#define CTX_FAR_EL1 0xb8
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#define CTX_AFSR0_EL1 0xc0
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#define CTX_AFSR1_EL1 0xc8
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#define CTX_CONTEXTIDR_EL1 0xd0
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#define CTX_VBAR_EL1 0xd8
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#define CTX_SCTLR_EL1 0x10
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#define CTX_ACTLR_EL1 0x18
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#define CTX_CPACR_EL1 0x20
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#define CTX_CSSELR_EL1 0x28
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#define CTX_SP_EL1 0x30
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#define CTX_ESR_EL1 0x38
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#define CTX_TTBR0_EL1 0x40
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#define CTX_TTBR1_EL1 0x48
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#define CTX_MAIR_EL1 0x50
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#define CTX_AMAIR_EL1 0x58
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#define CTX_TCR_EL1 0x60
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#define CTX_TPIDR_EL1 0x68
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#define CTX_TPIDR_EL0 0x70
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#define CTX_TPIDRRO_EL0 0x78
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#define CTX_PAR_EL1 0x80
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#define CTX_FAR_EL1 0x88
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#define CTX_AFSR0_EL1 0x90
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#define CTX_AFSR1_EL1 0x98
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#define CTX_CONTEXTIDR_EL1 0xa0
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#define CTX_VBAR_EL1 0xa8
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/*
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* If the platform is AArch64-only, there is no need to save and restore these
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* AArch32 registers.
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*/
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#if CTX_INCLUDE_AARCH32_REGS
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#define CTX_SPSR_ABT 0xb0
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#define CTX_SPSR_UND 0xb8
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#define CTX_SPSR_IRQ 0xc0
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#define CTX_SPSR_FIQ 0xc8
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#define CTX_DACR32_EL2 0xd0
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#define CTX_IFSR32_EL2 0xd8
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#define CTX_FP_FPEXC32_EL2 0xe0
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#define CTX_TIMER_SYSREGS_OFF 0xf0 /* Align to the next 16 byte boundary */
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#else
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#define CTX_TIMER_SYSREGS_OFF 0xb0
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#endif /* __CTX_INCLUDE_AARCH32_REGS__ */
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/*
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* If the timer registers aren't saved and restored, we don't have to reserve
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* space for them in the context
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*/
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#if NS_TIMER_SWITCH
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#define CTX_CNTP_CTL_EL0 0xe0
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#define CTX_CNTP_CVAL_EL0 0xe8
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#define CTX_CNTV_CTL_EL0 0xf0
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#define CTX_CNTV_CVAL_EL0 0xf8
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#define CTX_CNTKCTL_EL1 0x100
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#define CTX_FP_FPEXC32_EL2 0x108
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#define CTX_SYSREGS_END 0x110
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#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x0)
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#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x8)
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#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x10)
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#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x18)
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#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + 0x20)
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#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + 0x30) /* Align to the next 16 byte boundary */
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#else
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#define CTX_FP_FPEXC32_EL2 0xe0
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#define CTX_SYSREGS_END 0xf0
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#endif
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#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF
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#endif /* __NS_TIMER_SWITCH__ */
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the 'fp_regs'
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