Tegra194: se: fix multiple MISRA issues
This patch fixes violations for the following MISRA rules * Rule 8.4 "A compatible declaration shall be visible when an object or function with external linkage is defined" * Rule 10.1 "Operands shall not be of an inappropriate essential type" * Rule 10.6 "Both operands of an operator in which the usual arithmetic conversions are perdormed shall have the same essential type category" * Rule 17.7 "The value returned by a function having non-void return type shall be used" Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -15,6 +15,7 @@
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <se.h>
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#include <tegra_platform.h>
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#include "se_private.h"
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@ -54,7 +55,7 @@ static bool tegra_se_is_operation_complete(void)
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*/
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do {
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val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
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se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY);
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se_is_busy = ((val & CTX_SAVE_AUTO_SE_BUSY) != 0U);
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/* sleep until SE finishes */
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if (se_is_busy) {
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@ -186,7 +187,8 @@ int32_t tegra_se_suspend(void)
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assert(tegra_bpmp_ipc_init() == 0);
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/* Enable SE clock before SE context save */
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tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
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ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
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assert(ret == 0);
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/* save SE registers */
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se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
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@ -201,7 +203,8 @@ int32_t tegra_se_suspend(void)
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}
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/* Disable SE clock after SE context save */
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tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
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ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
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assert(ret == 0);
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return ret;
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}
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@ -211,11 +214,14 @@ int32_t tegra_se_suspend(void)
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*/
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void tegra_se_resume(void)
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{
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int32_t ret = 0;
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/* initialise communication channel with BPMP */
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assert(tegra_bpmp_ipc_init() == 0);
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/* Enable SE clock before SE context restore */
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tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
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ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
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assert(ret == 0);
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/*
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* When TZ takes over after System Resume, TZ should first reconfigure
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@ -229,5 +235,6 @@ void tegra_se_resume(void)
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mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
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/* Disable SE clock after SE context restore */
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tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
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ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
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assert(ret == 0);
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}
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@ -74,12 +74,12 @@
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static inline uint32_t tegra_se_read_32(uint32_t offset)
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{
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return mmio_read_32(TEGRA_SE0_BASE + offset);
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return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset));
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}
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static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
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{
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mmio_write_32(TEGRA_SE0_BASE + offset, val);
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mmio_write_32((uint32_t)(TEGRA_SE0_BASE + offset), val);
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}
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#endif /* SE_PRIVATE_H */
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