Merge changes I65450c63,I71d0aa82,Ia395eb32,I4aaed371 into integration
* changes: mediatek: mt8192: add rtc power off sequence mediatek: mt8192: Fix non-MISRA compliant code mediatek: mt8192: Fix non-MISRA compliant code mediatek: mt8192: Add MPU support
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
8fdebc945d
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@ -16,6 +16,7 @@
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#include <lib/coreboot.h>
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/* Platform Includes */
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#include <emi_mpu/emi_mpu.h>
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#include <gpio/mtgpio.h>
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#include <mt_gic_v3.h>
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#include <mt_timer.h>
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@ -89,6 +90,9 @@ void bl31_platform_setup(void)
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ERROR("Failed to set default dcm on!!\n");
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}
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/* MPU Init */
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emi_mpu_init();
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/* Initialize the GIC driver, CPU and distributor interfaces */
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mt_gic_driver_init();
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mt_gic_init();
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@ -0,0 +1,122 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <emi_mpu.h>
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#include <lib/mmio.h>
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/*
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* emi_mpu_set_region_protection: protect a region.
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* @start: start address of the region
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* @end: end address of the region
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* @access_permission: EMI MPU access permission
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* Return 0 for success, otherwise negative status code.
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*/
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static int _emi_mpu_set_protection(
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unsigned long start, unsigned long end,
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unsigned int apc)
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{
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unsigned int dgroup;
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unsigned int region;
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region = (start >> 24) & 0xFF;
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start &= 0x00FFFFFF;
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dgroup = (end >> 24) & 0xFF;
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end &= 0x00FFFFFF;
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if ((region >= EMI_MPU_REGION_NUM) || (dgroup > EMI_MPU_DGROUP_NUM)) {
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WARN("Region:%u or dgroup:%u is wrong!\n", region, dgroup);
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return -1;
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}
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apc &= 0x80FFFFFF;
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if ((start >= DRAM_OFFSET) && (end >= start)) {
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start -= DRAM_OFFSET;
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end -= DRAM_OFFSET;
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} else {
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WARN("start:0x%lx or end:0x%lx address is wrong!\n",
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start, end);
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return -2;
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}
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mmio_write_32(EMI_MPU_SA(region), start);
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mmio_write_32(EMI_MPU_EA(region), end);
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mmio_write_32(EMI_MPU_APC(region, dgroup), apc);
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return 0;
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}
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void dump_emi_mpu_regions(void)
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{
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unsigned long apc[EMI_MPU_DGROUP_NUM], sa, ea;
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int region, i;
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/* Only dump 8 regions(max: EMI_MPU_REGION_NUM --> 32) */
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for (region = 0; region < 8; ++region) {
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for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i)
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apc[i] = mmio_read_32(EMI_MPU_APC(region, i));
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sa = mmio_read_32(EMI_MPU_SA(region));
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ea = mmio_read_32(EMI_MPU_EA(region));
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WARN("region %d:\n", region);
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WARN("\tsa:0x%lx, ea:0x%lx, apc0: 0x%lx apc1: 0x%lx\n",
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sa, ea, apc[0], apc[1]);
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}
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}
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int emi_mpu_set_protection(struct emi_region_info_t *region_info)
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{
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unsigned long start, end;
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int i;
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if (region_info->region >= EMI_MPU_REGION_NUM)
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return -1;
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start = (unsigned long)(region_info->start >> EMI_MPU_ALIGN_BITS) |
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(region_info->region << 24);
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for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) {
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end = (unsigned long)(region_info->end >> EMI_MPU_ALIGN_BITS) |
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(i << 24);
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_emi_mpu_set_protection(start, end, region_info->apc[i]);
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}
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return 0;
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}
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void emi_mpu_init(void)
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{
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/* Set permission */
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struct emi_region_info_t region_info;
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/* PCE-e protect address(TODO) */
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region_info.start = 0x80000000ULL;
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region_info.end = 0x83FF0000ULL;
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region_info.region = 1;
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SET_ACCESS_PERMISSION(region_info.apc, 1,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
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FORBIDDEN, FORBIDDEN, NO_PROT,
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NO_PROT /*FORBIDDEN*/);
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emi_mpu_set_protection(®ion_info);
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/* Forbidden All */
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region_info.start = 0x40000000ULL; /* dram base addr */
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region_info.end = 0x1FFFF0000ULL;
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region_info.region = 2;
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SET_ACCESS_PERMISSION(region_info.apc, 1,
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NO_PROT, NO_PROT, NO_PROT, NO_PROT,
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NO_PROT, NO_PROT, NO_PROT, NO_PROT,
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NO_PROT, NO_PROT, NO_PROT, NO_PROT,
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NO_PROT, FORBIDDEN, NO_PROT, NO_PROT);
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emi_mpu_set_protection(®ion_info);
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dump_emi_mpu_regions();
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}
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@ -0,0 +1,102 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef EMI_MPU_H
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#define EMI_MPU_H
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#include <platform_def.h>
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#define EMI_MPUP (EMI_BASE + 0x01D8)
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#define EMI_MPUQ (EMI_BASE + 0x01E0)
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#define EMI_MPUR (EMI_BASE + 0x01E8)
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#define EMI_MPUS (EMI_BASE + 0x01F0)
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#define EMI_MPUT (EMI_BASE + 0x01F8)
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#define EMI_MPUY (EMI_BASE + 0x0220)
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#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000)
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#define EMI_MPUD0_ST (EMI_BASE + 0x0160)
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#define EMI_MPUD1_ST (EMI_BASE + 0x0164)
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#define EMI_MPUD2_ST (EMI_BASE + 0x0168)
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#define EMI_MPUD3_ST (EMI_BASE + 0x016C)
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#define EMI_MPUD0_ST2 (EMI_BASE + 0x0200)
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#define EMI_MPUD1_ST2 (EMI_BASE + 0x0204)
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#define EMI_MPUD2_ST2 (EMI_BASE + 0x0208)
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#define EMI_MPUD3_ST2 (EMI_BASE + 0x020C)
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#define EMI_PHY_OFFSET (0x40000000UL)
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#define NO_PROT (0)
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#define SEC_RW (1)
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#define SEC_RW_NSEC_R (2)
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#define SEC_RW_NSEC_W (3)
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#define SEC_R_NSEC_R (4)
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#define FORBIDDEN (5)
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#define SEC_R_NSEC_RW (6)
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#define SECURE_OS_MPU_REGION_ID (0)
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#define ATF_MPU_REGION_ID (1)
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#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
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#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
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#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region) * 4)
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#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region) * 4)
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#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
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#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region) * 4 + \
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(dgroup) * 0x100)
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#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
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#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + domain * 4)
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#define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
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#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + domain * 4)
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#define EMI_MPU_DOMAIN_NUM 16
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#define EMI_MPU_REGION_NUM 32
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#define EMI_MPU_ALIGN_BITS 16
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#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
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#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
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#if (EMI_MPU_DGROUP_NUM == 1)
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#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \
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do { \
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apc_ary[0] = 0; \
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apc_ary[0] = \
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(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \
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| (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \
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| (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \
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| (((unsigned int) d1) << 3) | ((unsigned int) d0) \
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| (((unsigned int) lock) << 31); \
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} while (0)
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#elif (EMI_MPU_DGROUP_NUM == 2)
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#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \
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d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \
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do { \
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apc_ary[1] = \
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(((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) \
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| (((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) \
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| (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) \
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| (((unsigned int) d9) << 3) | ((unsigned int) d8); \
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apc_ary[0] = \
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(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \
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| (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \
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| (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \
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| (((unsigned int) d1) << 3) | ((unsigned int) d0) \
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| (((unsigned int) lock) << 31); \
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} while (0)
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#endif
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struct emi_region_info_t {
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unsigned long long start;
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unsigned long long end;
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unsigned int region;
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unsigned long apc[EMI_MPU_DGROUP_NUM];
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};
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void emi_mpu_init(void);
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int emi_mpu_set_protection(struct emi_region_info_t *region_info);
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void dump_emi_mpu_regions(void);
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#endif /* __EMI_MPU_H */
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@ -39,15 +39,15 @@ void ptp3_init(unsigned int core)
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{
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unsigned int _core;
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if (core >= PTP3_CFG1_CPU_START_ID) {
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if (core < NR_PTP3_CFG1_CPU) {
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/* update ptp3_cfg1 */
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ptp3_write(
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ptp3_cfg1[core][PTP3_CFG_ADDR],
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ptp3_cfg1[core][PTP3_CFG_VALUE]);
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}
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/* Apply ptp3_cfg1 for core 0 to 7 */
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if (core < NR_PTP3_CFG1_CPU) {
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/* update ptp3_cfg1 */
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ptp3_write(
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ptp3_cfg1[core][PTP3_CFG_ADDR],
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ptp3_cfg1[core][PTP3_CFG_VALUE]);
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}
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/* Apply ptp3_cfg2 for core 4 to 7 */
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if (core >= PTP3_CFG2_CPU_START_ID) {
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_core = core - PTP3_CFG2_CPU_START_ID;
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@ -59,6 +59,7 @@ void ptp3_init(unsigned int core)
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}
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}
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/* Apply ptp3_cfg3 for core 4 to 7 */
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if (core >= PTP3_CFG3_CPU_START_ID) {
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_core = core - PTP3_CFG3_CPU_START_ID;
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@ -73,13 +74,11 @@ void ptp3_init(unsigned int core)
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void ptp3_deinit(unsigned int core)
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{
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if (core >= PTP3_CFG1_CPU_START_ID) {
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if (core < NR_PTP3_CFG1_CPU) {
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/* update ptp3_cfg1 */
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ptp3_write(
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ptp3_cfg1[core][PTP3_CFG_ADDR],
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ptp3_cfg1[core][PTP3_CFG_VALUE] &
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~PTP3_CFG1_MASK);
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}
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if (core < NR_PTP3_CFG1_CPU) {
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/* update ptp3_cfg1 */
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ptp3_write(
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ptp3_cfg1[core][PTP3_CFG_ADDR],
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ptp3_cfg1[core][PTP3_CFG_VALUE] &
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~PTP3_CFG1_MASK);
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}
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}
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|
|
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|
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@ -0,0 +1,148 @@
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
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*
|
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
|
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|
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <rtc.h>
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|
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|
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static void RTC_Config_Interface(uint32_t addr, uint16_t data,
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uint16_t mask, uint16_t shift)
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{
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uint16_t pmic_reg;
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pmic_reg = RTC_Read(addr);
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pmic_reg &= ~(mask << shift);
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pmic_reg |= (data << shift);
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RTC_Write(addr, pmic_reg);
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}
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static int32_t rtc_disable_2sec_reboot(void)
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{
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uint16_t reboot;
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|
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reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) &
|
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~RTC_BBPU_AUTO_PDN_SEL;
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RTC_Write(RTC_AL_SEC, reboot);
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|
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return RTC_Write_Trigger();
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}
|
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|
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static int32_t rtc_enable_k_eosc(void)
|
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{
|
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uint16_t alm_dow, alm_sec;
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int16_t ret;
|
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|
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/* Turning on eosc cali mode clock */
|
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RTC_Config_Interface(PMIC_RG_SCK_TOP_CKPDN_CON0_CLR, 1,
|
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PMIC_RG_RTC_EOSC32_CK_PDN_MASK,
|
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PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
|
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|
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alm_sec = RTC_Read(RTC_AL_SEC) & (~RTC_LPD_OPT_MASK);
|
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RTC_Write(RTC_AL_SEC, alm_sec);
|
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ret = RTC_Write_Trigger();
|
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if (ret == 0) {
|
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return 0;
|
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}
|
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|
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RTC_Write(RTC_CON, RTC_LPD_EN);
|
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ret = RTC_Write_Trigger();
|
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if (ret == 0) {
|
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return 0;
|
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}
|
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|
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RTC_Write(RTC_CON, RTC_LPD_RST);
|
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ret = RTC_Write_Trigger();
|
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if (ret == 0) {
|
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return 0;
|
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}
|
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|
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RTC_Write(RTC_CON, RTC_LPD_EN);
|
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ret = RTC_Write_Trigger();
|
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if (ret == 0) {
|
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return 0;
|
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}
|
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|
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RTC_Write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
|
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RTC_Write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
|
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ret = RTC_Write_Trigger();
|
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if (ret == 0) {
|
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return 0;
|
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}
|
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|
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/* set RTC EOSC calibration period = 8sec */
|
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alm_dow = (RTC_Read(RTC_AL_DOW) & (~RTC_RG_EOSC_CALI_TD_MASK)) |
|
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RTC_RG_EOSC_CALI_TD_8SEC;
|
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RTC_Write(RTC_AL_DOW, alm_dow);
|
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ret = RTC_Write_Trigger();
|
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if (ret == 0) {
|
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return 0;
|
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}
|
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|
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RTC_Write(RTC_BBPU,
|
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RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
|
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ret = RTC_Write_Trigger();
|
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if (ret == 0) {
|
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return 0;
|
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}
|
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|
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/* Enable K EOSC mode :use solution1 of eosc cali to fix mt6359p 32K*/
|
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RTC_Write(RTC_AL_YEA, (((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0)
|
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& (~RTC_K_EOSC_RSV_1)) | (RTC_K_EOSC_RSV_2)));
|
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ret = RTC_Write_Trigger();
|
||||
if (ret == 0) {
|
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return 0;
|
||||
}
|
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|
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INFO("[RTC] RTC_enable_k_eosc\n");
|
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|
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return 1;
|
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}
|
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|
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void rtc_power_off_sequence(void)
|
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{
|
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uint16_t bbpu;
|
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int16_t ret;
|
||||
|
||||
ret = rtc_disable_2sec_reboot();
|
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if (ret == 0) {
|
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return;
|
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}
|
||||
|
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ret = rtc_enable_k_eosc();
|
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if (ret == 0) {
|
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return;
|
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}
|
||||
|
||||
bbpu = RTC_BBPU_KEY | RTC_BBPU_PWREN;
|
||||
|
||||
if (Writeif_unlock() != 0) {
|
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RTC_Write(RTC_BBPU,
|
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bbpu | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR);
|
||||
RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW);
|
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ret = RTC_Write_Trigger();
|
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if (ret == 0) {
|
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return;
|
||||
}
|
||||
mdelay(1);
|
||||
|
||||
bbpu = RTC_Read(RTC_BBPU);
|
||||
|
||||
if (((bbpu & RTC_BBPU_RESET_ALARM) > 0) ||
|
||||
((bbpu & RTC_BBPU_RESET_SPAR) > 0)) {
|
||||
INFO("[RTC] timeout\n");
|
||||
}
|
||||
|
||||
bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
|
||||
RTC_Write(RTC_BBPU, bbpu);
|
||||
ret = RTC_Write_Trigger();
|
||||
if (ret == 0) {
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef RTC_H
|
||||
#define RTC_H
|
||||
|
||||
/* RTC registers */
|
||||
enum {
|
||||
RTC_BBPU = 0x0588,
|
||||
RTC_IRQ_STA = 0x058A,
|
||||
RTC_IRQ_EN = 0x058C,
|
||||
RTC_CII_EN = 0x058E
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_AL_SEC = 0x05A0,
|
||||
RTC_AL_MIN = 0x05A2,
|
||||
RTC_AL_HOU = 0x05A4,
|
||||
RTC_AL_DOM = 0x05A6,
|
||||
RTC_AL_DOW = 0x05A8,
|
||||
RTC_AL_MTH = 0x05AA,
|
||||
RTC_AL_YEA = 0x05AC,
|
||||
RTC_AL_MASK = 0x0590
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_OSC32CON = 0x05AE,
|
||||
RTC_CON = 0x05C4,
|
||||
RTC_WRTGR = 0x05C2
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_POWERKEY1 = 0x05B0,
|
||||
RTC_POWERKEY2 = 0x05B2
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_POWERKEY1_KEY = 0xA357,
|
||||
RTC_POWERKEY2_KEY = 0x67D2
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_PDN1 = 0x05B4,
|
||||
RTC_PDN2 = 0x05B6,
|
||||
RTC_SPAR0 = 0x05B8,
|
||||
RTC_SPAR1 = 0x05BA,
|
||||
RTC_PROT = 0x05BC,
|
||||
RTC_DIFF = 0x05BE,
|
||||
RTC_CALI = 0x05C0
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_OSC32CON_UNLOCK1 = 0x1A57,
|
||||
RTC_OSC32CON_UNLOCK2 = 0x2B68
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_LPD_EN = 0x0406,
|
||||
RTC_LPD_RST = 0x040E
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
|
||||
RTC_LPD_OPT_EOSC_LPD = 1U << 13,
|
||||
RTC_LPD_OPT_XOSC_LPD = 2U << 13,
|
||||
RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
|
||||
};
|
||||
|
||||
#define RTC_LPD_OPT_MASK (3U << 13)
|
||||
|
||||
enum {
|
||||
RTC_PROT_UNLOCK1 = 0x586A,
|
||||
RTC_PROT_UNLOCK2 = 0x9136
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_BBPU_PWREN = 1U << 0,
|
||||
RTC_BBPU_SPAR_SW = 1U << 1,
|
||||
RTC_BBPU_RESET_SPAR = 1U << 2,
|
||||
RTC_BBPU_RESET_ALARM = 1U << 3,
|
||||
RTC_BBPU_CLRPKY = 1U << 4,
|
||||
RTC_BBPU_RELOAD = 1U << 5,
|
||||
RTC_BBPU_CBUSY = 1U << 6
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_AL_MASK_SEC = 1U << 0,
|
||||
RTC_AL_MASK_MIN = 1U << 1,
|
||||
RTC_AL_MASK_HOU = 1U << 2,
|
||||
RTC_AL_MASK_DOM = 1U << 3,
|
||||
RTC_AL_MASK_DOW = 1U << 4,
|
||||
RTC_AL_MASK_MTH = 1U << 5,
|
||||
RTC_AL_MASK_YEA = 1U << 6
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
|
||||
RTC_BBPU_2SEC_CK_SEL = 1U << 7,
|
||||
RTC_BBPU_2SEC_EN = 1U << 8,
|
||||
RTC_BBPU_2SEC_MODE = 0x3 << 9,
|
||||
RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
|
||||
RTC_BBPU_2SEC_STAT_STA = 1U << 12
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_BBPU_KEY = 0x43 << 8
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_EMBCK_SRC_SEL = 1 << 8,
|
||||
RTC_EMBCK_SEL_MODE = 3 << 6,
|
||||
RTC_XOSC32_ENB = 1 << 5,
|
||||
RTC_REG_XOSC32_ENB = 1 << 15
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_K_EOSC_RSV_0 = 1 << 8,
|
||||
RTC_K_EOSC_RSV_1 = 1 << 9,
|
||||
RTC_K_EOSC_RSV_2 = 1 << 10
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_RG_EOSC_CALI_TD_1SEC = 3 << 5,
|
||||
RTC_RG_EOSC_CALI_TD_2SEC = 4 << 5,
|
||||
RTC_RG_EOSC_CALI_TD_4SEC = 5 << 5,
|
||||
RTC_RG_EOSC_CALI_TD_8SEC = 6 << 5,
|
||||
RTC_RG_EOSC_CALI_TD_16SEC = 7 << 5,
|
||||
RTC_RG_EOSC_CALI_TD_MASK = 7 << 5
|
||||
};
|
||||
|
||||
/* PMIC TOP Register Definition */
|
||||
enum {
|
||||
PMIC_RG_TOP_CON = 0x0020,
|
||||
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
|
||||
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
|
||||
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
|
||||
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
|
||||
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
|
||||
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
|
||||
};
|
||||
|
||||
/* PMIC SCK Register Definition */
|
||||
enum {
|
||||
PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x0514,
|
||||
PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x0516,
|
||||
PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x0518,
|
||||
PMIC_RG_EOSC_CALI_CON0 = 0x53A
|
||||
};
|
||||
|
||||
enum {
|
||||
PMIC_EOSC_CALI_START_ADDR = 0x53A
|
||||
};
|
||||
|
||||
enum {
|
||||
PMIC_EOSC_CALI_START_MASK = 0x1,
|
||||
PMIC_EOSC_CALI_START_SHIFT = 0
|
||||
};
|
||||
|
||||
/* PMIC DCXO Register Definition */
|
||||
enum {
|
||||
PMIC_RG_DCXO_CW00 = 0x0788,
|
||||
PMIC_RG_DCXO_CW02 = 0x0790,
|
||||
PMIC_RG_DCXO_CW08 = 0x079C,
|
||||
PMIC_RG_DCXO_CW09 = 0x079E,
|
||||
PMIC_RG_DCXO_CW09_CLR = 0x07A2,
|
||||
PMIC_RG_DCXO_CW10 = 0x07A4,
|
||||
PMIC_RG_DCXO_CW12 = 0x07A8,
|
||||
PMIC_RG_DCXO_CW13 = 0x07AA,
|
||||
PMIC_RG_DCXO_CW15 = 0x07AE,
|
||||
PMIC_RG_DCXO_CW19 = 0x07B6,
|
||||
};
|
||||
|
||||
enum {
|
||||
PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
|
||||
PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
|
||||
PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
|
||||
PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
|
||||
PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
|
||||
PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
|
||||
PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
|
||||
PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
|
||||
PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
|
||||
PMIC_RG_XO_EN32K_MAN_SHIFT = 0
|
||||
};
|
||||
|
||||
/* external API */
|
||||
uint16_t RTC_Read(uint32_t addr);
|
||||
void RTC_Write(uint32_t addr, uint16_t data);
|
||||
int32_t rtc_busy_wait(void);
|
||||
int32_t RTC_Write_Trigger(void);
|
||||
int32_t Writeif_unlock(void);
|
||||
void rtc_power_off_sequence(void);
|
||||
|
||||
#endif /* RTC_H */
|
||||
|
|
@ -30,6 +30,8 @@
|
|||
#define GPIO_BASE (IO_PHYS + 0x00005000)
|
||||
#define SPM_BASE (IO_PHYS + 0x00006000)
|
||||
#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
|
||||
#define EMI_BASE (IO_PHYS + 0x00219000)
|
||||
#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
|
||||
#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
|
||||
#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
|
||||
#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <plat_params.h>
|
||||
#include <plat_pm.h>
|
||||
#include <pmic.h>
|
||||
#include <rtc.h>
|
||||
|
||||
/*
|
||||
* Cluster state request:
|
||||
|
|
@ -297,10 +298,6 @@ static int plat_validate_power_state(unsigned int power_state,
|
|||
unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
|
||||
unsigned int cpu = plat_my_core_pos();
|
||||
|
||||
if (aff_lvl > PLAT_MAX_PWR_LVL) {
|
||||
return PSCI_E_INVALID_PARAMS;
|
||||
}
|
||||
|
||||
if (pstate == PSTATE_TYPE_STANDBY) {
|
||||
req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
|
||||
} else {
|
||||
|
|
@ -345,6 +342,7 @@ static void __dead2 plat_mtk_system_off(void)
|
|||
{
|
||||
INFO("MTK System Off\n");
|
||||
|
||||
rtc_power_off_sequence();
|
||||
pmic_power_off();
|
||||
|
||||
wfi();
|
||||
|
|
|
|||
|
|
@ -11,10 +11,12 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
|
|||
-I${MTK_PLAT_SOC}/include/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/dcm \
|
||||
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/gpio/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/pmic/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/ptp3/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/rtc/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/spmc/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/timer/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/uart/
|
||||
|
|
@ -38,6 +40,7 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
lib/cpus/aarch64/cortex_a76.S \
|
||||
plat/common/plat_gicv3.c \
|
||||
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
|
||||
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
|
||||
${MTK_PLAT}/common/drivers/uart/uart.c \
|
||||
${MTK_PLAT}/common/mtk_plat_common.c \
|
||||
${MTK_PLAT}/common/mtk_sip_svc.c \
|
||||
|
|
@ -46,6 +49,7 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
|
||||
${MTK_PLAT_SOC}/bl31_plat_setup.c \
|
||||
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
|
||||
${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
|
||||
${MTK_PLAT_SOC}/plat_pm.c \
|
||||
${MTK_PLAT_SOC}/plat_topology.c \
|
||||
${MTK_PLAT_SOC}/plat_mt_gic.c \
|
||||
|
|
@ -53,6 +57,7 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
${MTK_PLAT_SOC}/plat_sip_calls.c \
|
||||
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
|
||||
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
|
||||
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
|
||||
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
|
||||
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
|
||||
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
|
||||
|
|
|
|||
Loading…
Reference in New Issue