Merge changes from topic "yg/optee" into integration
* changes: stm32mp1: add OP-TEE support stm32mp1: fix TZC400 configuration against non-secure DDR stm32mp1: remove useless define stm32mp: split stm32mp_io_setup function
This commit is contained in:
Antonio Niño Díaz
TrustedFirmware Code Review
commit
932d029616
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@ -69,11 +69,15 @@ Boot sequence
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ROM code -> BL2 (compiled with BL2_AT_EL3) -> BL32 (SP_min) -> BL33 (U-Boot)
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or if Op-TEE is used:
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ROM code -> BL2 (compiled with BL2_AT_EL3) -> OP-TEE -> BL33 (U-Boot)
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Build Instructions
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------------------
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To build:
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To build with SP_min:
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.. code:: bash
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@ -83,6 +87,12 @@ To build:
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make DEVICE_TREE=stm32mp157c-ev1 all
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./tools/mkimage -T stm32image -a 0xC0100000 -e 0xC0100000 -d u-boot.bin u-boot.stm32
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To build TF-A with with Op-TEE support:
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.. code:: bash
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make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=optee
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The following build options are supported:
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- ``ENABLE_STACK_PROTECTOR``: To enable the stack protection.
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@ -54,10 +54,27 @@ static const io_block_dev_spec_t mmc_block_dev_spec = {
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static uintptr_t storage_dev_handle;
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static const io_dev_connector_t *mmc_dev_con;
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#ifdef AARCH32_SP_OPTEE
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static const struct stm32image_part_info optee_header_partition_spec = {
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.name = OPTEE_HEADER_IMAGE_NAME,
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.binary_type = OPTEE_HEADER_BINARY_TYPE,
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};
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static const struct stm32image_part_info optee_pager_partition_spec = {
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.name = OPTEE_PAGER_IMAGE_NAME,
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.binary_type = OPTEE_PAGER_BINARY_TYPE,
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};
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static const struct stm32image_part_info optee_paged_partition_spec = {
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.name = OPTEE_PAGED_IMAGE_NAME,
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.binary_type = OPTEE_PAGED_BINARY_TYPE,
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};
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#else
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static const io_block_spec_t bl32_block_spec = {
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.offset = BL32_BASE,
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.length = STM32MP_BL32_SIZE
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};
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#endif
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static const io_block_spec_t bl2_block_spec = {
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.offset = BL2_BASE,
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@ -71,6 +88,11 @@ static const struct stm32image_part_info bl33_partition_spec = {
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enum {
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IMG_IDX_BL33,
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#ifdef AARCH32_SP_OPTEE
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IMG_IDX_OPTEE_HEADER,
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IMG_IDX_OPTEE_PAGER,
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IMG_IDX_OPTEE_PAGED,
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#endif
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IMG_IDX_NUM
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};
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@ -80,6 +102,20 @@ static struct stm32image_device_info stm32image_dev_info_spec = {
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.name = BL33_IMAGE_NAME,
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.binary_type = BL33_BINARY_TYPE,
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},
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#ifdef AARCH32_SP_OPTEE
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.part_info[IMG_IDX_OPTEE_HEADER] = {
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.name = OPTEE_HEADER_IMAGE_NAME,
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.binary_type = OPTEE_HEADER_BINARY_TYPE,
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},
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.part_info[IMG_IDX_OPTEE_PAGER] = {
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.name = OPTEE_PAGER_IMAGE_NAME,
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.binary_type = OPTEE_PAGER_BINARY_TYPE,
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},
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.part_info[IMG_IDX_OPTEE_PAGED] = {
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.name = OPTEE_PAGED_IMAGE_NAME,
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.binary_type = OPTEE_PAGED_BINARY_TYPE,
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},
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#endif
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};
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static io_block_spec_t stm32image_block_spec = {
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@ -105,11 +141,29 @@ static const struct plat_io_policy policies[] = {
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.image_spec = (uintptr_t)&bl2_block_spec,
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.check = open_dummy
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},
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#ifdef AARCH32_SP_OPTEE
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[BL32_IMAGE_ID] = {
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.dev_handle = &image_dev_handle,
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.image_spec = (uintptr_t)&optee_header_partition_spec,
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.check = open_image
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},
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[BL32_EXTRA1_IMAGE_ID] = {
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.dev_handle = &image_dev_handle,
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.image_spec = (uintptr_t)&optee_pager_partition_spec,
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.check = open_image
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},
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[BL32_EXTRA2_IMAGE_ID] = {
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.dev_handle = &image_dev_handle,
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.image_spec = (uintptr_t)&optee_paged_partition_spec,
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.check = open_image
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},
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#else
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[BL32_IMAGE_ID] = {
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.dev_handle = &dummy_dev_handle,
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.image_spec = (uintptr_t)&bl32_block_spec,
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.check = open_dummy
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},
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#endif
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[BL33_IMAGE_ID] = {
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.dev_handle = &image_dev_handle,
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.image_spec = (uintptr_t)&bl33_partition_spec,
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@ -162,15 +216,99 @@ static void print_boot_device(boot_api_context_t *boot_context)
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}
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}
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void stm32mp_io_setup(void)
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static void boot_mmc(enum mmc_device_type mmc_dev_type,
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uint16_t boot_interface_instance)
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{
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int io_result __unused;
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uint8_t idx;
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struct stm32image_part_info *part;
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struct stm32_sdmmc2_params params;
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struct mmc_device_info device_info;
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uintptr_t mmc_default_instance;
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const partition_entry_t *entry;
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zeromem(&device_info, sizeof(struct mmc_device_info));
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zeromem(¶ms, sizeof(struct stm32_sdmmc2_params));
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device_info.mmc_dev_type = mmc_dev_type;
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switch (boot_interface_instance) {
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case 1:
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params.reg_base = STM32MP_SDMMC1_BASE;
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break;
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case 2:
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params.reg_base = STM32MP_SDMMC2_BASE;
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break;
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case 3:
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params.reg_base = STM32MP_SDMMC3_BASE;
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break;
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default:
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WARN("SDMMC instance not found, using default\n");
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if (mmc_dev_type == MMC_IS_SD) {
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params.reg_base = STM32MP_SDMMC1_BASE;
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} else {
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params.reg_base = STM32MP_SDMMC2_BASE;
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}
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break;
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}
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params.device_info = &device_info;
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if (stm32_sdmmc2_mmc_init(¶ms) != 0) {
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ERROR("SDMMC%u init failed\n", boot_interface_instance);
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panic();
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}
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/* Open MMC as a block device to read GPT table */
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io_result = register_io_dev_block(&mmc_dev_con);
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if (io_result != 0) {
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panic();
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}
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io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
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&storage_dev_handle);
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assert(io_result == 0);
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partition_init(GPT_IMAGE_ID);
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io_result = io_dev_close(storage_dev_handle);
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assert(io_result == 0);
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stm32image_dev_info_spec.device_size =
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stm32_sdmmc2_mmc_get_device_size();
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for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
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part = &stm32image_dev_info_spec.part_info[idx];
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entry = get_partition_entry(part->name);
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if (entry == NULL) {
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ERROR("Partition %s not found\n", part->name);
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panic();
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}
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part->part_offset = entry->start;
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part->bkp_offset = 0U;
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}
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/*
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* Re-open MMC with io_mmc, for better perfs compared to
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* io_block.
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*/
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io_result = register_io_dev_mmc(&mmc_dev_con);
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assert(io_result == 0);
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io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle);
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assert(io_result == 0);
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io_result = register_io_dev_stm32image(&stm32image_dev_con);
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assert(io_result == 0);
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io_result = io_dev_open(stm32image_dev_con,
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(uintptr_t)&stm32image_dev_info_spec,
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&image_dev_handle);
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assert(io_result == 0);
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}
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void stm32mp_io_setup(void)
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{
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int io_result __unused;
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boot_api_context_t *boot_context =
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(boot_api_context_t *)stm32mp_get_boot_ctx_address();
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@ -191,93 +329,12 @@ void stm32mp_io_setup(void)
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switch (boot_context->boot_interface_selected) {
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
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dmbsy();
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boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
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break;
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
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dmbsy();
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zeromem(&device_info, sizeof(struct mmc_device_info));
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zeromem(¶ms, sizeof(struct stm32_sdmmc2_params));
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if (boot_context->boot_interface_selected ==
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BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC) {
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device_info.mmc_dev_type = MMC_IS_EMMC;
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mmc_default_instance = STM32MP_SDMMC2_BASE;
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} else {
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device_info.mmc_dev_type = MMC_IS_SD;
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mmc_default_instance = STM32MP_SDMMC1_BASE;
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}
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switch (boot_context->boot_interface_instance) {
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case 1:
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params.reg_base = STM32MP_SDMMC1_BASE;
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break;
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case 2:
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params.reg_base = STM32MP_SDMMC2_BASE;
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break;
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case 3:
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params.reg_base = STM32MP_SDMMC3_BASE;
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break;
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default:
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WARN("SDMMC instance not found, using default\n");
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params.reg_base = mmc_default_instance;
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break;
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}
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params.device_info = &device_info;
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if (stm32_sdmmc2_mmc_init(¶ms) != 0) {
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ERROR("SDMMC%u init failed\n",
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boot_context->boot_interface_instance);
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panic();
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}
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/* Open MMC as a block device to read GPT table */
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io_result = register_io_dev_block(&mmc_dev_con);
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if (io_result != 0) {
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panic();
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}
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io_result = io_dev_open(mmc_dev_con,
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(uintptr_t)&mmc_block_dev_spec,
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&storage_dev_handle);
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assert(io_result == 0);
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partition_init(GPT_IMAGE_ID);
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io_result = io_dev_close(storage_dev_handle);
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assert(io_result == 0);
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stm32image_dev_info_spec.device_size =
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stm32_sdmmc2_mmc_get_device_size();
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for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
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part = &stm32image_dev_info_spec.part_info[idx];
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entry = get_partition_entry(part->name);
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if (entry == NULL) {
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ERROR("Partition %s not found\n",
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part->name);
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panic();
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}
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part->part_offset = entry->start;
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part->bkp_offset = 0U;
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}
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/*
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* Re-open MMC with io_mmc, for better perfs compared to
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* io_block.
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*/
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io_result = register_io_dev_mmc(&mmc_dev_con);
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assert(io_result == 0);
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io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle);
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assert(io_result == 0);
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io_result = register_io_dev_stm32image(&stm32image_dev_con);
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assert(io_result == 0);
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io_result = io_dev_open(stm32image_dev_con,
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(uintptr_t)&stm32image_dev_info_spec,
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&image_dev_handle);
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assert(io_result == 0);
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boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
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break;
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default:
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|
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@ -22,6 +22,7 @@
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#include <drivers/st/stm32mp1_pwr.h>
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#include <drivers/st/stm32mp1_ram.h>
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#include <lib/mmio.h>
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#include <lib/optee_utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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@ -136,7 +137,13 @@ void bl2_platform_setup(void)
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panic();
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}
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#ifdef AARCH32_SP_OPTEE
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INFO("BL2 runs OP-TEE setup\n");
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/* Initialize tzc400 after DDR initialization */
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stm32mp1_security_setup();
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#else
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INFO("BL2 runs SP_MIN setup\n");
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#endif
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}
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void bl2_el3_plat_arch_setup(void)
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|
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@ -154,11 +161,25 @@ void bl2_el3_plat_arch_setup(void)
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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|
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#ifdef AARCH32_SP_OPTEE
|
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/* OP-TEE image needs post load processing: keep RAM read/write */
|
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mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() -
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STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
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STM32MP_DDR_BASE + dt_get_ddr_size() -
|
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STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
|
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STM32MP_DDR_S_SIZE,
|
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MT_MEMORY | MT_RW | MT_SECURE);
|
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|
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mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
|
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STM32MP_OPTEE_SIZE,
|
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MT_MEMORY | MT_RW | MT_SECURE);
|
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#else
|
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/* Prevent corruption of preloaded BL32 */
|
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mmap_add_region(BL32_BASE, BL32_BASE,
|
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BL32_LIMIT - BL32_BASE,
|
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MT_MEMORY | MT_RO | MT_SECURE);
|
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|
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#endif
|
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/* Map non secure DDR for BL33 load and DDR training area restore */
|
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mmap_add_region(STM32MP_DDR_BASE,
|
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STM32MP_DDR_BASE,
|
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|
|
@ -261,3 +282,69 @@ skip_console_init:
|
|||
|
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stm32mp_io_setup();
|
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}
|
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|
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#if defined(AARCH32_SP_OPTEE)
|
||||
/*******************************************************************************
|
||||
* This function can be used by the platforms to update/use image
|
||||
* information for given `image_id`.
|
||||
******************************************************************************/
|
||||
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
||||
{
|
||||
int err = 0;
|
||||
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
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bl_mem_params_node_t *bl32_mem_params;
|
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bl_mem_params_node_t *pager_mem_params;
|
||||
bl_mem_params_node_t *paged_mem_params;
|
||||
|
||||
assert(bl_mem_params != NULL);
|
||||
|
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switch (image_id) {
|
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case BL32_IMAGE_ID:
|
||||
bl_mem_params->ep_info.pc =
|
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bl_mem_params->image_info.image_base;
|
||||
|
||||
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
|
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assert(pager_mem_params != NULL);
|
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pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
|
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pager_mem_params->image_info.image_max_size =
|
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STM32MP_OPTEE_SIZE;
|
||||
|
||||
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
|
||||
assert(paged_mem_params != NULL);
|
||||
paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
|
||||
(dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
|
||||
STM32MP_DDR_SHMEM_SIZE);
|
||||
paged_mem_params->image_info.image_max_size =
|
||||
STM32MP_DDR_S_SIZE;
|
||||
|
||||
err = parse_optee_header(&bl_mem_params->ep_info,
|
||||
&pager_mem_params->image_info,
|
||||
&paged_mem_params->image_info);
|
||||
if (err) {
|
||||
ERROR("OPTEE header parse error.\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
/* Set optee boot info from parsed header data */
|
||||
bl_mem_params->ep_info.pc =
|
||||
pager_mem_params->image_info.image_base;
|
||||
bl_mem_params->ep_info.args.arg0 =
|
||||
paged_mem_params->image_info.image_base;
|
||||
bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
|
||||
bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
|
||||
break;
|
||||
|
||||
case BL33_IMAGE_ID:
|
||||
bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
|
||||
assert(bl32_mem_params != NULL);
|
||||
bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Do nothing in default case */
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -25,6 +25,15 @@
|
|||
#define PLATFORM_STACK_SIZE 0xC00
|
||||
#endif
|
||||
|
||||
#ifdef AARCH32_SP_OPTEE
|
||||
#define OPTEE_HEADER_IMAGE_NAME "teeh"
|
||||
#define OPTEE_PAGED_IMAGE_NAME "teed"
|
||||
#define OPTEE_PAGER_IMAGE_NAME "teex"
|
||||
#define OPTEE_HEADER_BINARY_TYPE U(0x20)
|
||||
#define OPTEE_PAGER_BINARY_TYPE U(0x21)
|
||||
#define OPTEE_PAGED_BINARY_TYPE U(0x22)
|
||||
#endif
|
||||
|
||||
/* SSBL = second stage boot loader */
|
||||
#define BL33_IMAGE_NAME "ssbl"
|
||||
#define BL33_BINARY_TYPE U(0x0)
|
||||
|
|
@ -57,9 +66,11 @@
|
|||
/*******************************************************************************
|
||||
* BL32 specific defines.
|
||||
******************************************************************************/
|
||||
#ifndef AARCH32_SP_OPTEE
|
||||
#define BL32_BASE STM32MP_BL32_BASE
|
||||
#define BL32_LIMIT (STM32MP_BL32_BASE + \
|
||||
STM32MP_BL32_SIZE)
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* BL33 specific defines.
|
||||
|
|
|
|||
|
|
@ -27,7 +27,9 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
|
|||
VERSION_2, entry_point_info_t,
|
||||
SECURE | EXECUTABLE | EP_FIRST_EXE),
|
||||
|
||||
#if !defined(AARCH32_SP_OPTEE)
|
||||
.ep_info.pc = BL32_BASE,
|
||||
#endif
|
||||
.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
|
||||
SPSR_E_LITTLE,
|
||||
DISABLE_ALL_EXCEPTIONS),
|
||||
|
|
@ -35,13 +37,48 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
|
|||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_PLAT_SETUP),
|
||||
|
||||
#if defined(AARCH32_SP_OPTEE)
|
||||
/* optee header is loaded in SYSRAM above BL2 */
|
||||
.image_info.image_base = STM32MP_OPTEE_BASE,
|
||||
.image_info.image_max_size = STM32MP_OPTEE_SIZE,
|
||||
#else
|
||||
.image_info.image_base = BL32_BASE,
|
||||
.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
|
||||
|
||||
#endif
|
||||
.next_handoff_image_id = BL33_IMAGE_ID,
|
||||
},
|
||||
|
||||
#if defined(AARCH32_SP_OPTEE)
|
||||
/* Fill BL32 external 1 image related information */
|
||||
{
|
||||
.image_id = BL32_EXTRA1_IMAGE_ID,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||
VERSION_2, entry_point_info_t,
|
||||
SECURE | NON_EXECUTABLE),
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_SKIP_LOADING),
|
||||
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
},
|
||||
/* Fill BL32 external 2 image related information */
|
||||
{
|
||||
.image_id = BL32_EXTRA2_IMAGE_ID,
|
||||
|
||||
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
|
||||
VERSION_2, entry_point_info_t,
|
||||
SECURE | NON_EXECUTABLE),
|
||||
|
||||
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
|
||||
VERSION_2, image_info_t,
|
||||
IMAGE_ATTRIB_SKIP_LOADING),
|
||||
|
||||
.next_handoff_image_id = INVALID_IMAGE_ID,
|
||||
},
|
||||
#endif /* AARCH32_SP_OPTEE */
|
||||
|
||||
/* Fill BL33 related information */
|
||||
{
|
||||
.image_id = BL33_IMAGE_ID,
|
||||
|
|
|
|||
|
|
@ -18,7 +18,11 @@ WORKAROUND_CVE_2017_5715:= 0
|
|||
# Number of TF-A copies in the device
|
||||
STM32_TF_A_COPIES := 2
|
||||
$(eval $(call add_define,STM32_TF_A_COPIES))
|
||||
ifeq ($(AARCH32_SP),optee)
|
||||
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 4)))
|
||||
else
|
||||
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 1)))
|
||||
endif
|
||||
$(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
|
||||
|
||||
PLAT_INCLUDES := -Iplat/st/common/include/
|
||||
|
|
@ -84,6 +88,10 @@ BL2_SOURCES += common/desc_image_load.c \
|
|||
plat/st/stm32mp1/plat_bl2_mem_params_desc.c \
|
||||
plat/st/stm32mp1/plat_image_load.c
|
||||
|
||||
ifeq ($(AARCH32_SP),optee)
|
||||
BL2_SOURCES += lib/optee/optee_utils.c
|
||||
endif
|
||||
|
||||
# Macros and rules to build TF binary
|
||||
STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed
|
||||
STM32_DT_BASENAME := $(DTB_FILE_NAME:.dtb=)
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ SECTIONS
|
|||
*(.bl2_image*)
|
||||
__BL2_IMAGE_END__ = .;
|
||||
|
||||
#ifndef AARCH32_SP_OPTEE
|
||||
/*
|
||||
* bl32 will be settled by bl2.
|
||||
* The strongest and only alignment constraint is 8 words to simplify
|
||||
|
|
@ -67,6 +68,7 @@ SECTIONS
|
|||
__BL32_IMAGE_START__ = .;
|
||||
*(.bl32_image*)
|
||||
__BL32_IMAGE_END__ = .;
|
||||
#endif
|
||||
|
||||
__DATA_END__ = .;
|
||||
} >RAM
|
||||
|
|
|
|||
|
|
@ -34,7 +34,10 @@
|
|||
/* DDR configuration */
|
||||
#define STM32MP_DDR_BASE U(0xC0000000)
|
||||
#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
|
||||
#define STM32MP_DDR_SPEED_DFLT 528
|
||||
#ifdef AARCH32_SP_OPTEE
|
||||
#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
|
||||
#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
|
||||
#endif
|
||||
|
||||
/* DDR power initializations */
|
||||
#ifndef __ASSEMBLY__
|
||||
|
|
@ -57,21 +60,38 @@ enum ddr_type {
|
|||
(STM32MP_PARAM_LOAD_SIZE + \
|
||||
STM32MP_HEADER_SIZE))
|
||||
|
||||
#ifdef AARCH32_SP_OPTEE
|
||||
#define STM32MP_BL32_SIZE U(0)
|
||||
|
||||
#define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE
|
||||
|
||||
#define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \
|
||||
STM32MP_OPTEE_BASE)
|
||||
#else
|
||||
#if STACK_PROTECTOR_ENABLED
|
||||
#define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */
|
||||
#else
|
||||
#define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \
|
||||
STM32MP_SYSRAM_SIZE - \
|
||||
STM32MP_BL32_SIZE)
|
||||
|
||||
#ifdef AARCH32_SP_OPTEE
|
||||
#if STACK_PROTECTOR_ENABLED
|
||||
#define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */
|
||||
#else
|
||||
#define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */
|
||||
#endif
|
||||
#else
|
||||
#if STACK_PROTECTOR_ENABLED
|
||||
#define STM32MP_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */
|
||||
#else
|
||||
#define STM32MP_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
|
||||
STM32MP_BL2_SIZE)
|
||||
|
|
|
|||
|
|
@ -14,6 +14,19 @@
|
|||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <lib/mmio.h>
|
||||
|
||||
#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)
|
||||
|
||||
/*******************************************************************************
|
||||
* Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
|
||||
* and allow Non-Secure masters full access.
|
||||
|
|
@ -23,31 +36,55 @@ static void init_tzc400(void)
|
|||
unsigned long long region_base, region_top;
|
||||
unsigned long long ddr_base = STM32MP_DDR_BASE;
|
||||
unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
|
||||
unsigned long long ddr_top = ddr_base + (ddr_size - 1U);
|
||||
|
||||
tzc400_init(STM32MP1_TZC_BASE);
|
||||
|
||||
tzc400_disable_filters();
|
||||
|
||||
/* Region 1 set to cover all DRAM at 0xC000_0000. Apply the
|
||||
#ifdef AARCH32_SP_OPTEE
|
||||
/*
|
||||
* Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the
|
||||
* same configuration to all filters in the TZC.
|
||||
*/
|
||||
region_base = ddr_base;
|
||||
region_top = ddr_base + (ddr_size - 1U);
|
||||
region_top = ddr_top - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE;
|
||||
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
|
||||
region_base,
|
||||
region_top,
|
||||
TZC_REGION_S_RDWR,
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID));
|
||||
region_base,
|
||||
region_top,
|
||||
TZC_REGION_S_NONE,
|
||||
TZC_REGION_NSEC_ALL_ACCESS_RDWR);
|
||||
|
||||
/* Region 2 set to cover all secure DRAM. */
|
||||
region_base = region_top + 1U;
|
||||
region_top = ddr_top - STM32MP_DDR_SHMEM_SIZE;
|
||||
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 2,
|
||||
region_base,
|
||||
region_top,
|
||||
TZC_REGION_S_RDWR,
|
||||
0);
|
||||
|
||||
/* Region 3 set to cover non-secure shared memory DRAM. */
|
||||
region_base = region_top + 1U;
|
||||
region_top = ddr_top;
|
||||
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 3,
|
||||
region_base,
|
||||
region_top,
|
||||
TZC_REGION_S_NONE,
|
||||
TZC_REGION_NSEC_ALL_ACCESS_RDWR);
|
||||
#else
|
||||
/*
|
||||
* Region 1 set to cover all DRAM at 0xC000_0000. Apply the
|
||||
* same configuration to all filters in the TZC.
|
||||
*/
|
||||
region_base = ddr_base;
|
||||
region_top = ddr_top;
|
||||
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
|
||||
region_base,
|
||||
region_top,
|
||||
TZC_REGION_S_NONE,
|
||||
TZC_REGION_NSEC_ALL_ACCESS_RDWR);
|
||||
#endif
|
||||
|
||||
/* Raise an exception if a NS device tries to access secure memory */
|
||||
tzc400_set_action(TZC_ACTION_ERR);
|
||||
|
|
@ -69,15 +106,12 @@ static void early_init_tzc400(void)
|
|||
|
||||
tzc400_disable_filters();
|
||||
|
||||
/*
|
||||
* Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the
|
||||
* same configuration to all filters in the TZC.
|
||||
*/
|
||||
/* Region 1 set to cover Non-Secure DRAM at 0xC000_0000 */
|
||||
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
|
||||
STM32MP_DDR_BASE,
|
||||
STM32MP_DDR_BASE +
|
||||
(STM32MP_DDR_MAX_SIZE - 1U),
|
||||
TZC_REGION_S_RDWR,
|
||||
TZC_REGION_S_NONE,
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
|
||||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue