Merge changes from topic "pull-out-drivers" into integration
* changes: intel: Add ncore ccu driver intel: Fix watchdog driver structure intel: Fix qspi driver write config intel: Pull out common drivers into platform common
This commit is contained in:
Paul Beesley
TrustedFirmware Code Review
commit
93c77622a6
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@ -15,7 +15,7 @@
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#include <drivers/io/io_storage.h>
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#include <lib/utils.h>
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#include "drivers/qspi/cadence_qspi.h"
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#include "qspi/cadence_qspi.h"
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/* As we need to be able to keep state for seek, only one file can be open
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* at a time. Make this a structure and point to the entity->info. When we
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@ -0,0 +1,126 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <errno.h>
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#include <lib/mmio.h>
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#include "ncore_ccu.h"
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#include <platform_def.h>
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uint32_t poll_active_bit(uint32_t dir);
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static coh_ss_id_t subsystem_id;
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void get_subsystem_id(void)
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{
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uint32_t snoop_filter, directory, coh_agent;
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snoop_filter = CSIDR_NUM_SF(mmio_read_32(NCORE_CCU_CSR(NCORE_CSIDR)));
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directory = CSUIDR_NUM_DIR(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
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coh_agent = CSUIDR_NUM_CAI(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR)));
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subsystem_id.num_snoop_filter = snoop_filter + 1;
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subsystem_id.num_directory = directory;
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subsystem_id.num_coh_agent = coh_agent;
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}
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uint32_t directory_init(void)
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{
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uint32_t dir_sf_mtn, dir_sf_en;
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uint32_t dir, sf, ret;
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for (dir = 0; dir < subsystem_id.num_directory; dir++) {
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dir_sf_mtn = DIRECTORY_UNIT(dir, NCORE_DIRUSFMCR);
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dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER);
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for (sf = 0; sf < subsystem_id.num_snoop_filter; sf++) {
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/* Initialize All Entries */
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mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(sf));
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/* Poll Active Bit */
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ret = poll_active_bit(dir);
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if (ret != 0) {
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ERROR("Timeout during active bit polling");
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return -ETIMEDOUT;
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}
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/* Snoope Filter Enable */
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mmio_write_32(dir_sf_en, BIT(sf));
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}
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}
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return 0;
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}
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uint32_t coherent_agent_intfc_init(void)
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{
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uint32_t dir, ca, ca_id, ca_type, ca_snoop_en;
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for (dir = 0; dir < subsystem_id.num_directory; dir++) {
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ca_snoop_en = DIRECTORY_UNIT(dir, NCORE_DIRUCASER0);
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for (ca = 0; ca < subsystem_id.num_coh_agent; ca++) {
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ca_id = mmio_read_32(COH_AGENT_UNIT(ca, NCORE_CAIUIDR));
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/* Coh Agent Snoop Enable */
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if (CACHING_AGENT_BIT(ca_id))
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mmio_write_32(ca_snoop_en, BIT(ca));
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/* Coh Agent Snoop DVM Enable */
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ca_type = CACHING_AGENT_TYPE(ca_id);
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if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM)
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mmio_write_32(NCORE_CCU_CSR(NCORE_CSADSER0),
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BIT(ca));
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}
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}
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return 0;
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}
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uint32_t poll_active_bit(uint32_t dir)
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{
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uint32_t timeout = 80000;
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uint32_t poll_dir = DIRECTORY_UNIT(dir, NCORE_DIRUSFMAR);
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while (timeout > 0) {
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if (mmio_read_32(poll_dir) == 0)
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return 0;
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timeout--;
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}
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return -1;
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}
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void bypass_ocram_firewall(void)
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{
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mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
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OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
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}
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uint32_t init_ncore_ccu(void)
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{
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uint32_t status;
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get_subsystem_id();
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status = directory_init();
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status = coherent_agent_intfc_init();
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bypass_ocram_firewall();
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return status;
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}
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@ -0,0 +1,108 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NCORE_CCU_H
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#define NCORE_CCU_H
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#define NCORE_CCU_OFFSET 0xf7000000
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/* Coherent Sub-System Address Map */
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#define NCORE_CAIU_OFFSET 0x00000
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#define NCORE_CAIU_SIZE 0x01000
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#define NCORE_NCBU_OFFSET 0x60000
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#define NCORE_NCBU_SIZE 0x01000
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#define NCORE_DIRU_OFFSET 0x80000
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#define NCORE_DIRU_SIZE 0x01000
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#define NCORE_CMIU_OFFSET 0xc0000
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#define NCORE_CMIU_SIZE 0x01000
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#define NCORE_CSR_OFFSET 0xff000
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#define NCORE_CSADSERO 0x00040
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#define NCORE_CSUIDR 0x00ff8
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#define NCORE_CSIDR 0x00ffc
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/* Directory Unit Register Map */
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#define NCORE_DIRUSFER 0x00010
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#define NCORE_DIRUMRHER 0x00070
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#define NCORE_DIRUSFMCR 0x00080
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#define NCORE_DIRUSFMAR 0x00084
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/* Coherent Agent Interface Unit Register Map */
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#define NCORE_CAIUIDR 0x00ffc
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/* Snoop Enable Register */
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#define NCORE_DIRUCASER0 0x00040
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#define NCORE_DIRUCASER1 0x00044
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#define NCORE_DIRUCASER2 0x00048
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#define NCORE_DIRUCASER3 0x0004c
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#define NCORE_CSADSER0 0x00040
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#define NCORE_CSADSER1 0x00044
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#define NCORE_CSADSER2 0x00048
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#define NCORE_CSADSER3 0x0004c
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/* Protocols Definition */
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#define ACE_W_DVM 0
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#define ACE_L_W_DVM 1
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#define ACE_WO_DVM 2
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#define ACE_L_WO_DVM 3
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/* Bypass OC Ram Firewall */
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#define NCORE_FW_OCRAM_BLK_BASE 0x100200
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#define NCORE_FW_OCRAM_BLK_CGF1 0x04
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#define NCORE_FW_OCRAM_BLK_CGF2 0x08
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#define NCORE_FW_OCRAM_BLK_CGF3 0x0c
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#define NCORE_FW_OCRAM_BLK_CGF4 0x10
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#define OCRAM_PRIVILEGED_MASK BIT(29)
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#define OCRAM_SECURE_MASK BIT(30)
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/* Macros */
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#define NCORE_CCU_REG(base) (NCORE_CCU_OFFSET + (base))
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#define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\
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+ (reg))
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#define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\
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+ (reg))
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#define NCORE_CCU_CAI(reg) (NCORE_CCU_REG(NCORE_CAIU_OFFSET)\
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+ (reg))
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#define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\
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+ NCORE_DIRU_SIZE * (x))
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#define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\
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+ NCORE_CAIU_SIZE * (x))
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#define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\
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+ (reg))
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#define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24)
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#define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16)
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#define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8)
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#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0)
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#define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18)
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#define SNOOP_FILTER_ID(x) (((x) << 16))
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#define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15)
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#define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16)
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typedef struct coh_ss_id {
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uint8_t num_coh_mem;
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uint8_t num_directory;
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uint8_t num_non_coh_bridge;
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uint8_t num_coh_agent;
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uint8_t num_snoop_filter;
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} coh_ss_id_t;
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uint32_t init_ncore_ccu(void);
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#endif
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -65,13 +66,13 @@ int cad_qspi_set_read_config(uint32_t opcode, uint32_t instr_type,
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return 0;
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}
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int cat_qspi_set_write_config(uint32_t addr_type, uint32_t data_type,
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uint32_t mode_bit, uint32_t dummy_clk_cycle)
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int cad_qspi_set_write_config(uint32_t opcode, uint32_t addr_type,
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uint32_t data_type, uint32_t dummy_clk_cycle)
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{
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mmio_write_32(CAD_QSPI_OFFSET + CAD_QSPI_DEVWR,
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CAD_QSPI_DEV_OPCODE(opcode) |
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CAD_QSPI_DEV_ADDR_TYPE(addr_type) |
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CAD_QSPI_DEV_DATA_TYPE(data_type) |
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CAD_QSPI_DEV_MODE_BIT(mode_bit) |
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CAD_QSPI_DEV_DUMMY_CLK_CYCLE(dummy_clk_cycle));
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return 0;
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@ -161,7 +162,7 @@ int cad_qspi_stig_read_cmd(uint32_t opcode, uint32_t dummy, uint32_t num_bytes,
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CAD_QSPI_FLASHCMD_NUMDUMMYBYTES(dummy);
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if (cad_qspi_stig_cmd_helper(cad_qspi_cs, cmd)) {
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ERROR("failed to send stig cmd");
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ERROR("failed to send stig cmd\n");
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return -1;
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}
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@ -249,6 +250,8 @@ int cad_qspi_n25q_enable(void)
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cad_qspi_set_read_config(QSPI_FAST_READ, CAD_QSPI_INST_SINGLE,
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CAD_QSPI_ADDR_FASTREAD, CAT_QSPI_ADDR_SINGLE_IO, 1,
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0);
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cad_qspi_set_write_config(QSPI_WRITE, 0, 0, 0);
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return 0;
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}
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@ -512,7 +515,7 @@ int cad_qspi_init(uint32_t desired_clk_freq, uint32_t clk_phase,
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INFO("Initializing Qspi\n");
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if (cad_qspi_idle() == 0) {
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ERROR("device not idle");
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ERROR("device not idle\n");
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return -1;
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}
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@ -587,8 +590,9 @@ int cad_qspi_init(uint32_t desired_clk_freq, uint32_t clk_phase,
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return -1;
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}
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cad_qspi_configure_dev_size(S10_QSPI_ADDR_BYTES,
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S10_QSPI_BYTES_PER_DEV, S10_BYTES_PER_BLOCK);
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cad_qspi_configure_dev_size(INTEL_QSPI_ADDR_BYTES,
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INTEL_QSPI_BYTES_PER_DEV,
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INTEL_BYTES_PER_BLOCK);
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INFO("Flash size: %d Bytes\n", qspi_device_size);
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@ -689,13 +693,13 @@ int cad_qspi_read(void *buffer, uint32_t offset, uint32_t size)
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((long) ((int *)buffer) & 0x3) ||
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(offset & 0x3) ||
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(size & 0x3)) {
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ERROR("Invalid read parameter");
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ERROR("Invalid read parameter\n");
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return -1;
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}
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if (CAD_QSPI_INDRD_RD_STAT(mmio_read_32(CAD_QSPI_OFFSET +
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CAD_QSPI_INDRD))) {
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ERROR("Read in progress");
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ERROR("Read in progress\n");
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return -1;
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}
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@ -1,11 +1,12 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CAD_QSPI_H__
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#define __CAD_QSPI_H__
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#ifndef CAD_QSPI_H
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#define CAD_QSPI_H
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#define CAD_QSPI_MICRON_N25Q_SUPPORT 1
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@ -146,12 +147,14 @@
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#define CAD_QSPI_SUBSECTOR_SIZE 0x1000
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#define S10_QSPI_ADDR_BYTES 2
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#define S10_QSPI_BYTES_PER_DEV 256
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#define S10_BYTES_PER_BLOCK 16
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#define INTEL_QSPI_ADDR_BYTES 2
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#define INTEL_QSPI_BYTES_PER_DEV 256
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#define INTEL_BYTES_PER_BLOCK 16
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#define QSPI_FAST_READ 0xb
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#define QSPI_WRITE 0x2
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// QSPI CONFIGURATIONS
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#define QSPI_CONFIG_CPOL 1
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@ -28,10 +28,10 @@ void watchdog_info(void)
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void watchdog_status(void)
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{
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if (mmio_read_32(WDT_CR) & 1) {
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INFO("Watchdog Timer in currently enabled\n");
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INFO("Watchdog Timer is currently enabled\n");
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INFO("Current Counter : 0x%x\r\n", mmio_read_32(WDT_CCVR));
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} else {
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INFO("Watchdog Timer in currently disabled\n");
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INFO("Watchdog Timer is currently disabled\n");
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}
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}
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@ -49,10 +49,5 @@ void watchdog_init(int watchdog_clk)
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mmio_write_32(WDT_TORR, (cycles_i << 4) | cycles_i);
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watchdog_enable();
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}
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void watchdog_enable(void)
|
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{
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mmio_write_32(WDT_CR, WDT_CR_RMOD|WDT_CR_EN);
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}
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@ -4,8 +4,8 @@
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* SPDX-License-Identifier: BSD-3-Clause
|
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*/
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#ifndef __CAD_WATCHDOG_H__
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#define __CAD_WATCHDOG_H__
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#ifndef CAD_WATCHDOG_H
|
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#define CAD_WATCHDOG_H
|
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#define WDT_BASE (0xFFD00200)
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#define WDT_REG_SIZE_OFFSET (0x4)
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@ -32,7 +32,6 @@
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|
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void watchdog_init(int watchdog_clk);
|
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void watchdog_enable(void);
|
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void watchdog_info(void);
|
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void watchdog_status(void);
|
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void watchdog_sw_rst(void);
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|
|
@ -31,8 +31,8 @@
|
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#include "s10_pinmux.h"
|
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#include "aarch64/stratix10_private.h"
|
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#include "include/s10_mailbox.h"
|
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#include "drivers/qspi/cadence_qspi.h"
|
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#include "drivers/wdt/watchdog.h"
|
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#include "qspi/cadence_qspi.h"
|
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#include "wdt/watchdog.h"
|
||||
|
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|
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const mmap_region_t plat_stratix10_mmap[] = {
|
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|
|
|
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|
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@ -7,6 +7,7 @@
|
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PLAT_INCLUDES := \
|
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-Iplat/intel/soc/stratix10/ \
|
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-Iplat/intel/soc/stratix10/include/ \
|
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-Iplat/intel/soc/common/drivers/
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := \
|
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lib/xlat_tables/xlat_tables_common.c \
|
||||
|
|
@ -46,8 +47,8 @@ BL2_SOURCES += \
|
|||
plat/intel/soc/stratix10/soc/s10_system_manager.c \
|
||||
common/desc_image_load.c \
|
||||
plat/intel/soc/stratix10/soc/s10_mailbox.c \
|
||||
plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.c \
|
||||
plat/intel/soc/stratix10/drivers/wdt/watchdog.c
|
||||
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
|
||||
plat/intel/soc/common/drivers/wdt/watchdog.c
|
||||
|
||||
BL31_SOURCES += drivers/arm/cci/cci.c \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
|
|
|
|||
Loading…
Reference in New Issue