Merge changes from topic "a3700-comphy-fixes-1" into integration
* changes: refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants refactor(drivers/marvell/comphy-3700): rename Lane Status 1 register constants refactor(drivers/marvell/comphy-3700): rename Miscellaneous Control register constants refactor(drivers/marvell/comphy-3700): rename Idle Sync Enable register constants refactor(drivers/marvell/comphy-3700): unify Generation Settings register values refactor(drivers/marvell/comphy-3700): unify Generation Settings register names refactor(drivers/marvell/comphy-3700): drop _ADDR suffixes refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes refactor(drivers/marvell/comphy-3700): move and add comment for COMPHY_RESERVED_REG refactor(drivers/marvell/comphy-3700): move Miscellaneous Control 0 register definition refactor(drivers/marvell/comphy-3700): rename PHY_GEN_USB3_5G to PHY_GEN_MAX_USB3_5G refactor(drivers/marvell/comphy-3700): rename Digital Loopback Enable register constant fix(drivers/marvell/comphy): change reg_set() / reg_set16() to update semantics fix(drivers/marvell/comphy-3700): use reg_set() according to update semantics fix(drivers/marvell/comphy-3700): fix comments about selector register values fix(drivers/marvell/comphy-3700): fix comment about COMPHY status register fix(drivers/marvell/comphy-3700): fix reference clock selection value names fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant fix(drivers/marvell/comphy-3700): fix SerDes frequency register value name fix(drivers/marvell/comphy-3700): fix Generation Setting registers names fix(drivers/marvell/comphy-3700): fix PIN_PU_IVREF register name
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
9554a186a7
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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* Copyright (C) 2018-2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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@ -301,7 +301,7 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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}
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/* Clear phy isolation mode to make it work in normal mode */
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offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
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offset = COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE);
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/* 0. Check the Polarity invert bits */
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@ -310,21 +310,21 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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if (invert & COMPHY_POLARITY_RXD_INVERT)
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data |= RXD_INVERT_BIT;
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offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
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offset = COMPHY_SYNC_PATTERN + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
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RXD_INVERT_BIT);
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/* 1. Select 40-bit data width width */
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offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET;
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offset = COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET;
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comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
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SEL_DATA_WIDTH_MASK);
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/* 2. Select reference clock(25M) and PHY mode (SATA) */
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offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
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if (get_ref_clk() == 40)
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ref_clk = REF_CLOCK_SPEED_40M;
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ref_clk = REF_FREF_SEL_SERDES_40MHZ;
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else
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ref_clk = REF_CLOCK_SPEED_25M;
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ref_clk = REF_FREF_SEL_SERDES_25MHZ;
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comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
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REF_FREF_SEL_MASK | PHY_MODE_MASK);
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@ -352,7 +352,7 @@ static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
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/* Polling status */
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mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
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COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
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COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET);
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ret = polling_with_timeout(comphy_indir_regs +
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COMPHY_LANE2_INDIR_DATA_OFFSET,
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@ -401,8 +401,8 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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* PHY TXP/TXN output to idle state during PHY initialization
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* 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
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*/
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data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;
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mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
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data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;
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mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
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PIN_PU_TX_BIT;
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offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
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reg_set(offset, data, mask);
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@ -422,8 +422,8 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET;
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} else if (mode == COMPHY_2500BASEX_MODE) {
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/* 2500Base-X, SerDes speed 3.125G */
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data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET;
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data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET;
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data |= SD_SPEED_3_125_G << GEN_RX_SEL_OFFSET;
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data |= SD_SPEED_3_125_G << GEN_TX_SEL_OFFSET;
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} else {
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/* Other rates are not supported */
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ERROR("unsupported SGMII speed on comphy lane%d\n",
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@ -450,16 +450,16 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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*/
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data = 0;
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mask = PHY_REF_CLK_SEL;
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reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask);
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reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_CTRL0, sd_ip_addr), data, mask);
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/*
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* 9. Set correct reference clock frequency in COMPHY register
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* REF_FREF_SEL.
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*/
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if (get_ref_clk() == 40)
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data = REF_CLOCK_SPEED_50M;
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data = REF_FREF_SEL_SERDES_50MHZ;
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else
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data = REF_CLOCK_SPEED_25M;
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data = REF_FREF_SEL_SERDES_25MHZ;
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mask = REF_FREF_SEL_MASK;
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reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask);
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@ -477,7 +477,8 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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*/
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data = DATA_WIDTH_10BIT;
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mask = SEL_DATA_WIDTH_MASK;
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reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask);
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reg_set16(SGMIIPHY_ADDR(COMPHY_DIG_LOOPBACK_EN, sd_ip_addr),
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data, mask);
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/*
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* 12. As long as DFE function needs to be enabled in any mode,
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@ -523,7 +524,7 @@ static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
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if (invert & COMPHY_POLARITY_RXD_INVERT)
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data |= RXD_INVERT_BIT;
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mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
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reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask);
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reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN, sd_ip_addr), data, mask);
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/*
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* 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
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@ -645,68 +646,68 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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*/
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mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
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CFG_TX_ALIGN_POS_MASK;
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
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mask);
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usb3_reg_set(reg_base, COMPHY_LANE_CFG0, PRD_TXDEEMPH0_MASK, mask);
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/*
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* 2. Set BIT0: enable transmitter in high impedance mode
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* Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
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* Set BIT6: Tx detect Rx at HiZ mode
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* Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
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* together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register
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* together with bit 0 of COMPHY_LANE_CFG0 register
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*/
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mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
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TX_ELEC_IDLE_MODE_EN;
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data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask);
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usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask);
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/*
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* 3. Set Spread Spectrum Clock Enabled
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*/
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usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR,
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usb3_reg_set(reg_base, COMPHY_LANE_CFG4,
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SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
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/*
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* 4. Set Override Margining Controls From the MAC:
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* Use margining signals from lane configuration
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*/
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usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR,
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usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL,
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MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK);
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/*
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* 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
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* set Mode Clock Source = PCLK is generated from REFCLK
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*/
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usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0,
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(MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
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BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
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usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0,
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(MODE_CLK_SRC | BUNDLE_PERIOD_SEL |
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BUNDLE_PERIOD_SCALE_MASK | BUNDLE_SAMPLE_CTRL |
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PLL_READY_DLY_MASK));
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/*
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* 6. Set G2 Spread Spectrum Clock Amplitude at 4K
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*/
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usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2,
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G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK);
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usb3_reg_set(reg_base, COMPHY_GEN2_SET2,
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GS2_TX_SSC_AMP_VALUE_20, GS2_TX_SSC_AMP_MASK);
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/*
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* 7. Unset G3 Spread Spectrum Clock Amplitude
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* set G3 TX and RX Register Master Current Select
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*/
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mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK |
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RSVD_PH03FH_6_0_MASK;
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usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3,
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G3_VREG_RXTX_MAS_ISET_60U, mask);
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mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK |
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GS2_RSVD_6_0_MASK;
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usb3_reg_set(reg_base, COMPHY_GEN3_SET2,
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GS2_VREG_RXTX_MAS_ISET_60U, mask);
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/*
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* 8. Check crystal jumper setting and program the Power and PLL Control
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* accordingly Change RX wait
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*/
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if (get_ref_clk() == 40) {
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ref_clk = REF_CLOCK_SPEED_40M;
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ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;
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cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT;
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} else {
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/* 25 MHz */
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ref_clk = USB3_REF_CLOCK_SPEED_25M;
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ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;
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cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT;
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}
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@ -720,24 +721,24 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
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CFG_PM_RXDLOZ_WAIT_MASK;
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data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
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usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask);
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usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1, data, mask);
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/*
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* 9. Enable idle sync
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*/
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data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
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usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK);
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data = IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN;
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usb3_reg_set(reg_base, COMPHY_IDLE_SYNC_EN, data, REG_16_BIT_MASK);
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/*
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* 10. Enable the output of 500M clock
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*/
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data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
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usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK);
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data = MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN;
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usb3_reg_set(reg_base, COMPHY_MISC_CTRL0, data, REG_16_BIT_MASK);
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/*
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* 11. Set 20-bit data width
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*/
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usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT,
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usb3_reg_set(reg_base, COMPHY_DIG_LOOPBACK_EN, DATA_WIDTH_20BIT,
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REG_16_BIT_MASK);
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/*
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@ -758,32 +759,31 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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data |= RXD_INVERT_BIT;
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}
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mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
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usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask);
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usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN, data, mask);
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/*
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* 14. Set max speed generation to USB3.0 5Gbps
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*/
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usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G,
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usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN, PHY_GEN_MAX_USB3_5G,
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PHY_GEN_MAX_MASK);
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/*
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* 15. Set capacitor value for FFE gain peaking to 0xF
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*/
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usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3,
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COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK);
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usb3_reg_set(reg_base, COMPHY_GEN2_SET3,
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GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK);
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/*
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* 16. Release SW reset
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*/
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data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
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usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data,
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REG_16_BIT_MASK);
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usb3_reg_set(reg_base, COMPHY_RST_CLK_CTRL, data, REG_16_BIT_MASK);
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/* Wait for > 55 us to allow PCLK be enabled */
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udelay(PLL_SET_DELAY_US);
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if (comphy_index == COMPHY_LANE2) {
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data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
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data = COMPHY_LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET;
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mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
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data);
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@ -791,7 +791,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
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ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
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COMPHY_PLL_TIMEOUT, REG_32BIT);
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} else {
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ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base,
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ret = polling_with_timeout(LANE_STAT1_ADDR(USB3) + reg_base,
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TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
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COMPHY_PLL_TIMEOUT, REG_16BIT);
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}
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@ -826,11 +826,11 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
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USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);
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/* 2. Select 20 bit SERDES interface. */
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reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
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reg_set16(CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
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CFG_SEL_20B, CFG_SEL_20B);
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/* 3. Force to use reg setting for PCIe mode */
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reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR,
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reg_set16(MISC_CTRL1_ADDR(PCIE) + COMPHY_SD_ADDR,
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SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
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/* 4. Change RX wait */
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|
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@ -840,12 +840,12 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
|
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CFG_PM_RXDLOZ_WAIT_MASK));
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/* 5. Enable idle sync */
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reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
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UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK);
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reg_set16(IDLE_SYNC_EN_ADDR(PCIE) + COMPHY_SD_ADDR,
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IDLE_SYNC_EN_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK);
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/* 6. Enable the output of 100M/125M/500M clock */
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reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR,
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MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
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reg_set16(MISC_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
|
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MISC_CTRL0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
|
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REG_16_BIT_MASK);
|
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/*
|
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|
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@ -859,9 +859,9 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
|
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*/
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|
||||
if (get_ref_clk() == 40)
|
||||
ref_clk = REF_CLOCK_SPEED_40M;
|
||||
ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;
|
||||
else
|
||||
ref_clk = PCIE_REF_CLOCK_SPEED_25M;
|
||||
ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;
|
||||
|
||||
reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
|
||||
(PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
|
||||
|
|
@ -881,17 +881,17 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
|
|||
data |= RXD_INVERT_BIT;
|
||||
}
|
||||
mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
|
||||
reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
|
||||
reg_set16(SYNC_PATTERN_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
|
||||
|
||||
/* 11. Release SW reset */
|
||||
reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
|
||||
MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32,
|
||||
SOFT_RESET | MODE_REFDIV);
|
||||
data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;
|
||||
mask = data | SOFT_RESET | MODE_REFDIV_MASK;
|
||||
reg_set16(RST_CLK_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
|
||||
|
||||
/* Wait for > 55 us to allow PCLK be enabled */
|
||||
udelay(PLL_SET_DELAY_US);
|
||||
|
||||
ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR,
|
||||
ret = polling_with_timeout(LANE_STAT1_ADDR(PCIE) + COMPHY_SD_ADDR,
|
||||
TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
|
||||
COMPHY_PLL_TIMEOUT, REG_16BIT);
|
||||
if (ret) {
|
||||
|
|
@ -961,7 +961,7 @@ static int mvebu_a3700_comphy_sata_power_off(void)
|
|||
debug_enter();
|
||||
|
||||
/* Set phy isolation mode */
|
||||
offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
|
||||
offset = COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
|
||||
comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
|
||||
PHY_ISOLATE_MODE);
|
||||
|
||||
|
|
@ -1025,7 +1025,7 @@ static int mvebu_a3700_comphy_sata_is_pll_locked(void)
|
|||
|
||||
/* Polling status */
|
||||
mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
|
||||
COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
|
||||
COMPHY_DIG_LOOPBACK_EN + SATAPHY_LANE2_REG_BASE_OFFSET);
|
||||
addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET;
|
||||
data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT,
|
||||
COMPHY_PLL_TIMEOUT, REG_32BIT);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
|
|
@ -13,11 +13,11 @@
|
|||
#define REG_16_BIT_MASK 0xFFFF
|
||||
|
||||
#define COMPHY_SELECTOR_PHY_REG 0xFC
|
||||
/* bit0: 0: Lane0 is GBE0; 1: Lane1 is PCIE */
|
||||
/* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIE */
|
||||
#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0)
|
||||
/* bit4: 0: Lane1 is GBE1; 1: Lane1 is USB3 */
|
||||
/* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
|
||||
#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
|
||||
/* bit8: 0: Lane1 is USB, Lane2 is SATA; 1: Lane2 is USB3 */
|
||||
/* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
|
||||
#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8)
|
||||
|
||||
/* SATA PHY register offset */
|
||||
|
|
@ -53,12 +53,11 @@ enum {
|
|||
#define PLL_LOCK_BIT BIT(8)
|
||||
#define REF_FREF_SEL_OFFSET 0
|
||||
#define REF_FREF_SEL_MASK (0x1F << REF_FREF_SEL_OFFSET)
|
||||
#define REF_CLOCK_SPEED_25M (0x1 << REF_FREF_SEL_OFFSET)
|
||||
#define REF_CLOCK_SPEED_30M (0x2 << REF_FREF_SEL_OFFSET)
|
||||
#define PCIE_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
|
||||
#define USB3_REF_CLOCK_SPEED_25M REF_CLOCK_SPEED_30M
|
||||
#define REF_CLOCK_SPEED_40M (0x3 << REF_FREF_SEL_OFFSET)
|
||||
#define REF_CLOCK_SPEED_50M (0x4 << REF_FREF_SEL_OFFSET)
|
||||
#define REF_FREF_SEL_SERDES_25MHZ (0x1 << REF_FREF_SEL_OFFSET)
|
||||
#define REF_FREF_SEL_SERDES_40MHZ (0x3 << REF_FREF_SEL_OFFSET)
|
||||
#define REF_FREF_SEL_SERDES_50MHZ (0x4 << REF_FREF_SEL_OFFSET)
|
||||
#define REF_FREF_SEL_PCIE_USB3_25MHZ (0x2 << REF_FREF_SEL_OFFSET)
|
||||
#define REF_FREF_SEL_PCIE_USB3_40MHZ (0x3 << REF_FREF_SEL_OFFSET)
|
||||
#define PHY_MODE_OFFSET 5
|
||||
#define PHY_MODE_MASK (7 << PHY_MODE_OFFSET)
|
||||
#define PHY_MODE_SATA (0x0 << PHY_MODE_OFFSET)
|
||||
|
|
@ -73,11 +72,9 @@ enum {
|
|||
#define SPEED_PLL_MASK (0x3F << SPEED_PLL_OFFSET)
|
||||
#define SPEED_PLL_VALUE_16 (0x10 << SPEED_PLL_OFFSET)
|
||||
|
||||
#define COMPHY_RESERVED_REG 0x0E
|
||||
#define PHYCTRL_FRM_PIN_BIT BIT(13)
|
||||
|
||||
#define COMPHY_LOOPBACK_REG0 0x23
|
||||
#define DIG_LB_EN_ADDR(unit) (COMPHY_LOOPBACK_REG0 * PHY_SHFT(unit))
|
||||
#define COMPHY_DIG_LOOPBACK_EN 0x23
|
||||
#define DIG_LOOPBACK_EN_ADDR(unit) (COMPHY_DIG_LOOPBACK_EN * \
|
||||
PHY_SHFT(unit))
|
||||
#define SEL_DATA_WIDTH_OFFSET 10
|
||||
#define SEL_DATA_WIDTH_MASK (0x3 << SEL_DATA_WIDTH_OFFSET)
|
||||
#define DATA_WIDTH_10BIT (0x0 << SEL_DATA_WIDTH_OFFSET)
|
||||
|
|
@ -85,80 +82,71 @@ enum {
|
|||
#define DATA_WIDTH_40BIT (0x2 << SEL_DATA_WIDTH_OFFSET)
|
||||
#define PLL_READY_TX_BIT BIT(4)
|
||||
|
||||
#define COMPHY_SYNC_PATTERN_REG 0x24
|
||||
#define SYNC_PATTERN_REG_ADDR(unit) (COMPHY_SYNC_PATTERN_REG * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_SYNC_PATTERN 0x24
|
||||
#define SYNC_PATTERN_ADDR(unit) (COMPHY_SYNC_PATTERN * PHY_SHFT(unit))
|
||||
#define TXD_INVERT_BIT BIT(10)
|
||||
#define RXD_INVERT_BIT BIT(11)
|
||||
|
||||
#define COMPHY_SYNC_MASK_GEN_REG 0x25
|
||||
#define COMPHY_SYNC_MASK_GEN 0x25
|
||||
#define PHY_GEN_MAX_OFFSET 10
|
||||
#define PHY_GEN_MAX_MASK (3 << PHY_GEN_MAX_OFFSET)
|
||||
#define PHY_GEN_USB3_5G (1 << PHY_GEN_MAX_OFFSET)
|
||||
#define PHY_GEN_MAX_USB3_5G (1 << PHY_GEN_MAX_OFFSET)
|
||||
|
||||
#define COMPHY_ISOLATION_CTRL_REG 0x26
|
||||
#define ISOLATION_CTRL_REG_ADDR(unit) (COMPHY_ISOLATION_CTRL_REG * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_ISOLATION_CTRL 0x26
|
||||
#define ISOLATION_CTRL_ADDR(unit) (COMPHY_ISOLATION_REG * PHY_SHFT(unit))
|
||||
#define PHY_ISOLATE_MODE BIT(15)
|
||||
|
||||
#define COMPHY_MISC_REG0_ADDR 0x4F
|
||||
#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit))
|
||||
#define COMPHY_GEN2_SET2 0x3e
|
||||
#define GEN2_SET2_ADDR(unit) (COMPHY_GEN2_SET2 * PHY_SHFT(unit))
|
||||
#define GS2_TX_SSC_AMP_VALUE_20 BIT(14)
|
||||
#define GS2_TX_SSC_AMP_OFF 9
|
||||
#define GS2_TX_SSC_AMP_LEN 7
|
||||
#define GS2_TX_SSC_AMP_MASK (((1 << GS2_TX_SSC_AMP_LEN) - 1) << \
|
||||
GS2_TX_SSC_AMP_OFF)
|
||||
#define GS2_VREG_RXTX_MAS_ISET_OFF 7
|
||||
#define GS2_VREG_RXTX_MAS_ISET_60U (0 << GS2_VREG_RXTX_MAS_ISET_OFF)
|
||||
#define GS2_VREG_RXTX_MAS_ISET_80U (1 << GS2_VREG_RXTX_MAS_ISET_OFF)
|
||||
#define GS2_VREG_RXTX_MAS_ISET_100U (2 << GS2_VREG_RXTX_MAS_ISET_OFF)
|
||||
#define GS2_VREG_RXTX_MAS_ISET_120U (3 << GS2_VREG_RXTX_MAS_ISET_OFF)
|
||||
#define GS2_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
|
||||
#define GS2_RSVD_6_0_OFF 0
|
||||
#define GS2_RSVD_6_0_LEN 7
|
||||
#define GS2_RSVD_6_0_MASK (((1 << GS2_RSVD_6_0_LEN) - 1) << \
|
||||
GS2_RSVD_6_0_OFF)
|
||||
|
||||
#define COMPHY_GEN3_SET2 0x3f
|
||||
#define GEN3_SET2_ADDR(unit) (COMPHY_GEN3_SET2 * PHY_SHFT(unit))
|
||||
|
||||
#define COMPHY_IDLE_SYNC_EN 0x48
|
||||
#define IDLE_SYNC_EN_ADDR(unit) (COMPHY_IDLE_SYNC_EN * PHY_SHFT(unit))
|
||||
#define IDLE_SYNC_EN BIT(12)
|
||||
#define IDLE_SYNC_EN_DEFAULT_VALUE 0x60
|
||||
|
||||
#define COMPHY_MISC_CTRL0 0x4F
|
||||
#define MISC_CTRL0_ADDR(unit) (COMPHY_MISC_CTRL0 * PHY_SHFT(unit))
|
||||
#define CLK100M_125M_EN BIT(4)
|
||||
#define TXDCLK_2X_SEL BIT(6)
|
||||
#define CLK500M_EN BIT(7)
|
||||
#define PHY_REF_CLK_SEL BIT(10)
|
||||
#define MISC_REG0_DEFAULT_VALUE 0xA00D
|
||||
#define MISC_CTRL0_DEFAULT_VALUE 0xA00D
|
||||
|
||||
#define COMPHY_REG_GEN2_SET_2 0x3e
|
||||
#define GEN2_SETTING_2_ADDR(unit) (COMPHY_REG_GEN2_SET_2 * PHY_SHFT(unit))
|
||||
#define G2_TX_SSC_AMP_VALUE_20 BIT(14)
|
||||
#define G2_TX_SSC_AMP_OFF 9
|
||||
#define G2_TX_SSC_AMP_LEN 7
|
||||
#define G2_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
|
||||
G2_TX_SSC_AMP_OFF)
|
||||
|
||||
#define COMPHY_REG_GEN2_SET_3 0x3f
|
||||
#define GEN2_SETTING_3_ADDR(unit) (COMPHY_REG_GEN2_SET_3 * PHY_SHFT(unit))
|
||||
#define G3_TX_SSC_AMP_OFF 9
|
||||
#define G3_TX_SSC_AMP_LEN 7
|
||||
#define G3_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
|
||||
G2_TX_SSC_AMP_OFF)
|
||||
#define G3_VREG_RXTX_MAS_ISET_OFF 7
|
||||
#define G3_VREG_RXTX_MAS_ISET_60U (0 << G3_VREG_RXTX_MAS_ISET_OFF)
|
||||
#define G3_VREG_RXTX_MAS_ISET_80U (1 << G3_VREG_RXTX_MAS_ISET_OFF)
|
||||
#define G3_VREG_RXTX_MAS_ISET_100U (2 << G3_VREG_RXTX_MAS_ISET_OFF)
|
||||
#define G3_VREG_RXTX_MAS_ISET_120U (3 << G3_VREG_RXTX_MAS_ISET_OFF)
|
||||
#define G3_VREG_RXTX_MAS_ISET_MASK (BIT(7) | BIT(8))
|
||||
#define RSVD_PH03FH_6_0_OFF 0
|
||||
#define RSVD_PH03FH_6_0_LEN 7
|
||||
#define RSVD_PH03FH_6_0_MASK (((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
|
||||
RSVD_PH03FH_6_0_OFF)
|
||||
|
||||
#define COMPHY_REG_UNIT_CTRL_ADDR 0x48
|
||||
#define UNIT_CTRL_ADDR(unit) (COMPHY_REG_UNIT_CTRL_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define IDLE_SYNC_EN BIT(12)
|
||||
#define UNIT_CTRL_DEFAULT_VALUE 0x60
|
||||
|
||||
#define COMPHY_MISC_REG1_ADDR 0x73
|
||||
#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1_ADDR * PHY_SHFT(unit))
|
||||
#define COMPHY_MISC_CTRL1 0x73
|
||||
#define MISC_CTRL1_ADDR(unit) (COMPHY_MISC_CTRL1 * PHY_SHFT(unit))
|
||||
#define SEL_BITS_PCIE_FORCE BIT(15)
|
||||
|
||||
#define COMPHY_REG_GEN3_SETTINGS_3 0x112
|
||||
#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF
|
||||
#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF
|
||||
#define COMPHY_GEN2_SET3 0x112
|
||||
#define GS3_FFE_CAP_SEL_MASK 0xF
|
||||
#define GS3_FFE_CAP_SEL_VALUE 0xF
|
||||
|
||||
#define COMPHY_REG_LANE_CFG0_ADDR 0x180
|
||||
#define LANE_CFG0_ADDR(unit) (COMPHY_REG_LANE_CFG0_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_LANE_CFG0 0x180
|
||||
#define LANE_CFG0_ADDR(unit) (COMPHY_LANE_CFG0 * PHY_SHFT(unit))
|
||||
#define PRD_TXDEEMPH0_MASK BIT(0)
|
||||
#define PRD_TXMARGIN_MASK (BIT(1) | BIT(2) | BIT(3))
|
||||
#define PRD_TXSWING_MASK BIT(4)
|
||||
#define CFG_TX_ALIGN_POS_MASK (BIT(5) | BIT(6) | BIT(7) | BIT(8))
|
||||
|
||||
#define COMPHY_REG_LANE_CFG1_ADDR 0x181
|
||||
#define LANE_CFG1_ADDR(unit) (COMPHY_REG_LANE_CFG1_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_LANE_CFG1 0x181
|
||||
#define LANE_CFG1_ADDR(unit) (COMPHY_LANE_CFG1 * PHY_SHFT(unit))
|
||||
#define PRD_TXDEEMPH1_MASK BIT(15)
|
||||
#define USE_MAX_PLL_RATE_EN BIT(9)
|
||||
#define TX_DET_RX_MODE BIT(6)
|
||||
|
|
@ -166,21 +154,17 @@ enum {
|
|||
#define GEN2_TX_DATA_DLY_DEFT (2 << 3)
|
||||
#define TX_ELEC_IDLE_MODE_EN BIT(0)
|
||||
|
||||
#define COMPHY_REG_LANE_STATUS1_ADDR 0x183
|
||||
#define LANE_STATUS1_ADDR(unit) (COMPHY_REG_LANE_STATUS1_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_LANE_STAT1 0x183
|
||||
#define LANE_STAT1_ADDR(unit) (COMPHY_LANE_STAT1 * PHY_SHFT(unit))
|
||||
#define TXDCLK_PCLK_EN BIT(0)
|
||||
|
||||
#define COMPHY_REG_LANE_CFG4_ADDR 0x188
|
||||
#define LANE_CFG4_ADDR(unit) (COMPHY_REG_LANE_CFG4_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_LANE_CFG4 0x188
|
||||
#define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4 * PHY_SHFT(unit))
|
||||
#define SPREAD_SPECTRUM_CLK_EN BIT(7)
|
||||
|
||||
#define COMPHY_REG_GLOB_PHY_CTRL0_ADDR 0x1C1
|
||||
#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_REG_GLOB_PHY_CTRL0_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_RST_CLK_CTRL 0x1C1
|
||||
#define RST_CLK_CTRL_ADDR(unit) (COMPHY_RST_CLK_CTRL * PHY_SHFT(unit))
|
||||
#define SOFT_RESET BIT(0)
|
||||
#define MODE_REFDIV 0x30
|
||||
#define MODE_CORE_CLK_FREQ_SEL BIT(9)
|
||||
#define MODE_PIPE_WIDTH_32 BIT(3)
|
||||
#define MODE_REFDIV_OFFSET 4
|
||||
|
|
@ -188,24 +172,21 @@ enum {
|
|||
#define MODE_REFDIV_MASK (0x3 << MODE_REFDIV_OFFSET)
|
||||
#define MODE_REFDIV_BY_4 (0x2 << MODE_REFDIV_OFFSET)
|
||||
|
||||
#define COMPHY_REG_TEST_MODE_CTRL_ADDR 0x1C2
|
||||
#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_REG_TEST_MODE_CTRL_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_TEST_MODE_CTRL 0x1C2
|
||||
#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_TEST_MODE_CTRL * PHY_SHFT(unit))
|
||||
#define MODE_MARGIN_OVERRIDE BIT(2)
|
||||
|
||||
#define COMPHY_REG_GLOB_CLK_SRC_LO_ADDR 0x1C3
|
||||
#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_REG_GLOB_CLK_SRC_LO_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_CLK_SRC_LO 0x1C3
|
||||
#define CLK_SRC_LO_ADDR(unit) (COMPHY_CLK_SRC_LO * PHY_SHFT(unit))
|
||||
#define MODE_CLK_SRC BIT(0)
|
||||
#define BUNDLE_PERIOD_SEL BIT(1)
|
||||
#define BUNDLE_PERIOD_SCALE (BIT(2) | BIT(3))
|
||||
#define BUNDLE_PERIOD_SCALE_MASK (BIT(2) | BIT(3))
|
||||
#define BUNDLE_SAMPLE_CTRL BIT(4)
|
||||
#define PLL_READY_DLY (BIT(5) | BIT(6) | BIT(7))
|
||||
#define PLL_READY_DLY_MASK (BIT(5) | BIT(6) | BIT(7))
|
||||
#define CFG_SEL_20B BIT(15)
|
||||
|
||||
#define COMPHY_REG_PWR_MGM_TIM1_ADDR 0x1D0
|
||||
#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_REG_PWR_MGM_TIM1_ADDR * \
|
||||
PHY_SHFT(unit))
|
||||
#define COMPHY_PWR_MGM_TIM1 0x1D0
|
||||
#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_PWR_MGM_TIM1 * PHY_SHFT(unit))
|
||||
#define CFG_PM_OSCCLK_WAIT_OFF 12
|
||||
#define CFG_PM_OSCCLK_WAIT_LEN 4
|
||||
#define CFG_PM_OSCCLK_WAIT_MASK (((1 << CFG_PM_OSCCLK_WAIT_LEN) - 1) \
|
||||
|
|
@ -222,9 +203,18 @@ enum {
|
|||
#define CFG_PM_RXDLOZ_WAIT_7_UNIT (7 << CFG_PM_RXDLOZ_WAIT_OFF)
|
||||
#define CFG_PM_RXDLOZ_WAIT_12_UNIT (0xC << CFG_PM_RXDLOZ_WAIT_OFF)
|
||||
|
||||
/*
|
||||
* This register is not from PHY lane register space. It only exists in the
|
||||
* indirect register space, before the actual PHY lane 2 registers. So the
|
||||
* offset is absolute, not relative to SATAPHY_LANE2_REG_BASE_OFFSET.
|
||||
* It is used only for SATA PHY initialization.
|
||||
*/
|
||||
#define COMPHY_RESERVED_REG 0x0E
|
||||
#define PHYCTRL_FRM_PIN_BIT BIT(13)
|
||||
|
||||
/* SGMII */
|
||||
#define COMPHY_PHY_CFG1_OFFSET(lane) ((1 - (lane)) * 0x28)
|
||||
#define PIN_PU_IVEREF_BIT BIT(1)
|
||||
#define PIN_PU_IVREF_BIT BIT(1)
|
||||
#define PIN_RESET_CORE_BIT BIT(11)
|
||||
#define PIN_RESET_COMPHY_BIT BIT(12)
|
||||
#define PIN_PU_PLL_BIT BIT(16)
|
||||
|
|
@ -237,11 +227,11 @@ enum {
|
|||
#define GEN_TX_SEL_MASK (0xF << GEN_TX_SEL_OFFSET)
|
||||
#define PHY_RX_INIT_BIT BIT(30)
|
||||
#define SD_SPEED_1_25_G 0x6
|
||||
#define SD_SPEED_2_5_G 0x8
|
||||
#define SD_SPEED_3_125_G 0x8
|
||||
|
||||
/* COMPHY status reg:
|
||||
* lane0: PCIe/GbE0 PHY Status 1
|
||||
* lane1: USB3/GbE1 PHY Status 1
|
||||
* lane0: USB3/GbE1 PHY Status 1
|
||||
* lane1: PCIe/GbE0 PHY Status 1
|
||||
*/
|
||||
#define COMPHY_PHY_STATUS_OFFSET(lane) (0x18 + (1 - (lane)) * 0x28)
|
||||
#define PHY_RX_INIT_DONE_BIT BIT(0)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
* Copyright (C) 2018-2021 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
|
|
@ -147,7 +147,7 @@ static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask)
|
|||
debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
|
||||
addr, data, mask);
|
||||
debug("old value = 0x%x ==> ", mmio_read_32(addr));
|
||||
mmio_clrsetbits_32(addr, mask, data);
|
||||
mmio_clrsetbits_32(addr, mask, data & mask);
|
||||
|
||||
debug("new val 0x%x\n", mmio_read_32(addr));
|
||||
}
|
||||
|
|
@ -159,7 +159,7 @@ static inline void __unused reg_set16(uintptr_t addr, uint16_t data,
|
|||
debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
|
||||
addr, data, mask);
|
||||
debug("old value = 0x%x ==> ", mmio_read_16(addr));
|
||||
mmio_clrsetbits_16(addr, mask, data);
|
||||
mmio_clrsetbits_16(addr, mask, data & mask);
|
||||
|
||||
debug("new val 0x%x\n", mmio_read_16(addr));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue