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refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants 

The constants BUNDLE_PERIOD_SCALE and PLL_READY_DLY refer to two
multi-bit registers within the Clock Source Low register. These
constants are used as masks for those registers (and values are not
defined since we are writing zeros to them).

Give them the _MASK suffix.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Id469d0ab4c755d2d6a0150a1ade33dd9d0293667
This commit is contained in:
Marek Behún 2021-12-08 01:33:38 +01:00
parent e585c84ce5
commit e62ae2e27d
2 changed files with 5 additions and 4 deletions
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5
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -678,8 +678,9 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
* set Mode Clock Source = PCLK is generated from REFCLK
*/
usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0,
(MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
(MODE_CLK_SRC | BUNDLE_PERIOD_SEL |
BUNDLE_PERIOD_SCALE_MASK | BUNDLE_SAMPLE_CTRL |
PLL_READY_DLY_MASK));
/*
* 6. Set G2 Spread Spectrum Clock Amplitude at 4K

4
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -180,9 +180,9 @@ enum {
#define CLK_SRC_LO_ADDR(unit) (COMPHY_CLK_SRC_LO * PHY_SHFT(unit))
#define MODE_CLK_SRC BIT(0)
#define BUNDLE_PERIOD_SEL BIT(1)
#define BUNDLE_PERIOD_SCALE (BIT(2) | BIT(3))
#define BUNDLE_PERIOD_SCALE_MASK (BIT(2) | BIT(3))
#define BUNDLE_SAMPLE_CTRL BIT(4)
#define PLL_READY_DLY (BIT(5) | BIT(6) | BIT(7))
#define PLL_READY_DLY_MASK (BIT(5) | BIT(6) | BIT(7))
#define CFG_SEL_20B BIT(15)
#define COMPHY_PWR_MGM_TIM1 0x1D0