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refactor(drivers/marvell/comphy-3700): rename Clock Source Low register constants 

The register at offset 0x1C3 is called Clock Source Low in functional
specification, but we use constant name GLOB_CLK_SRC_LO. Rename it to
RST_CLK_CTRL instead.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: If7ca460cb166f3828678e1e09c4e6caf5bb77770
This commit is contained in:
Marek Behún 2021-12-08 01:29:50 +01:00
parent 6a14ac780f
commit e585c84ce5
2 changed files with 4 additions and 5 deletions
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4
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -677,7 +677,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
* 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
* set Mode Clock Source = PCLK is generated from REFCLK
*/
usb3_reg_set(reg_base, COMPHY_GLOB_CLK_SRC_LO, 0x0,
usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0,
(MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
@ -825,7 +825,7 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);
/* 2. Select 20 bit SERDES interface. */
reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
reg_set16(CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
CFG_SEL_20B, CFG_SEL_20B);
/* 3. Force to use reg setting for PCIe mode */

5
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -176,9 +176,8 @@ enum {
#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_TEST_MODE_CTRL * PHY_SHFT(unit))
#define MODE_MARGIN_OVERRIDE BIT(2)
#define COMPHY_GLOB_CLK_SRC_LO 0x1C3
#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_GLOB_CLK_SRC_LO * \
PHY_SHFT(unit))
#define COMPHY_CLK_SRC_LO 0x1C3
#define CLK_SRC_LO_ADDR(unit) (COMPHY_CLK_SRC_LO * PHY_SHFT(unit))
#define MODE_CLK_SRC BIT(0)
#define BUNDLE_PERIOD_SEL BIT(1)
#define BUNDLE_PERIOD_SCALE (BIT(2) | BIT(3))