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refactor(drivers/marvell/comphy-3700): rename Reset and Clock Control register constants 

The register at offset 0x1C1 is called Reset and Clock Control in
functional specification, but we use constant name GLOB_PHY_CTRL0.
Rename it to RST_CLK_CTRL instead.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I5dac8913bd0686d4f5bd74b91cb7d07ba06df72b
This commit is contained in:
Marek Behún 2021-12-08 01:27:38 +01:00
parent 6eb043791e
commit 6a14ac780f
2 changed files with 4 additions and 4 deletions
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4
drivers/marvell/comphy/phy-comphy-3700.c
View File

@ -776,7 +776,7 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
* 16. Release SW reset
*/
data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
usb3_reg_set(reg_base, COMPHY_GLOB_PHY_CTRL0, data, REG_16_BIT_MASK);
usb3_reg_set(reg_base, COMPHY_RST_CLK_CTRL, data, REG_16_BIT_MASK);
/* Wait for > 55 us to allow PCLK be enabled */
udelay(PLL_SET_DELAY_US);
@ -885,7 +885,7 @@ static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
/* 11. Release SW reset */
data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;
mask = data | SOFT_RESET | MODE_REFDIV_MASK;
reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
reg_set16(RST_CLK_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
/* Wait for > 55 us to allow PCLK be enabled */
udelay(PLL_SET_DELAY_US);

4
drivers/marvell/comphy/phy-comphy-3700.h
View File

@ -162,8 +162,8 @@ enum {
#define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4 * PHY_SHFT(unit))
#define SPREAD_SPECTRUM_CLK_EN BIT(7)
#define COMPHY_GLOB_PHY_CTRL0 0x1C1
#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_GLOB_PHY_CTRL0 * PHY_SHFT(unit))
#define COMPHY_RST_CLK_CTRL 0x1C1
#define RST_CLK_CTRL_ADDR(unit) (COMPHY_RST_CLK_CTRL * PHY_SHFT(unit))
#define SOFT_RESET BIT(0)
#define MODE_CORE_CLK_FREQ_SEL BIT(9)
#define MODE_PIPE_WIDTH_32 BIT(3)