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allwinner: Add R_PRCM security setup for H6 

H6 has a reorganized R_PRCM compared to A64/H5, with the security switch
at a different offset. Until now, we did not notice, because the switch
has no effect unless the secure mode e-fuse is blown.

Since we are adding more platform-specific CCU registers, move them to
their own header, and out of the memory map (where they do not belong).

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie77476db0515080954eaa2e32bf6c3de657cda86
This commit is contained in:
Samuel Holland 2020-12-13 21:44:54 -06:00
parent 852e494075
commit 978a824091
5 changed files with 30 additions and 4 deletions
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4
plat/allwinner/common/sunxi_security.c
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@ -7,6 +7,7 @@
#include <common/debug.h>
#include <lib/mmio.h>
#include <sunxi_ccu.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
@ -16,7 +17,6 @@
#define SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc)
#endif
#define R_PRCM_SEC_SWITCH_REG 0x1d0
#define DMA_SEC_REG 0x20
/*
@ -40,7 +40,7 @@ void sunxi_security_setup(void)
mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);
/* Set R_PRCM bus clocks to non-secure */
mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x1);
mmio_write_32(SUNXI_R_PRCM_SEC_SWITCH_REG, 0x1);
/* Set all DMA channels (16 max.) to non-secure */
mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff);

14
plat/allwinner/sun50i_a64/include/sunxi_ccu.h Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SUNXI_CCU_H
#define SUNXI_CCU_H
#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x02f0)
#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x01d0)
#endif /* SUNXI_CCU_H */

1
plat/allwinner/sun50i_a64/include/sunxi_mmap.h
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@ -36,7 +36,6 @@
#define SUNXI_MSGBOX_BASE 0x01c17000
#define SUNXI_SPINLOCK_BASE 0x01c18000
#define SUNXI_CCU_BASE 0x01c20000
#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x2f0)
#define SUNXI_PIO_BASE 0x01c20800
#define SUNXI_TIMER_BASE 0x01c20c00
#define SUNXI_WDOG_BASE 0x01c20ca0

14
plat/allwinner/sun50i_h6/include/sunxi_ccu.h Normal file
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@ -0,0 +1,14 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SUNXI_CCU_H
#define SUNXI_CCU_H
#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00)
#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290)
#endif /* SUNXI_CCU_H */

1
plat/allwinner/sun50i_h6/include/sunxi_mmap.h
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@ -30,7 +30,6 @@
#define SUNXI_DMA_BASE 0x03002000
#define SUNXI_MSGBOX_BASE 0x03003000
#define SUNXI_CCU_BASE 0x03001000
#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0xf00)
#define SUNXI_PIO_BASE 0x0300b000
#define SUNXI_TIMER_BASE 0x03009000
#define SUNXI_WDOG_BASE 0x030090a0