Merge "drivers: arm: gicv3: auto-detect presence of GIC600-AE" into integration
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commit
99c447f440
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -20,26 +21,27 @@
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#include "gicv3_private.h"
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/* GIC-600 specific register offsets */
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#define GICR_PWRR 0x24
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#define IIDR_MODEL_ARM_GIC_600 0x0200043b
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#define GICR_PWRR 0x24
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#define IIDR_MODEL_ARM_GIC_600 (0x0200043b)
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#define IIDR_MODEL_ARM_GIC_600AE (0x0300043b)
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/* GICR_PWRR fields */
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#define PWRR_RDPD_SHIFT 0
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#define PWRR_RDAG_SHIFT 1
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#define PWRR_RDGPD_SHIFT 2
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#define PWRR_RDGPO_SHIFT 3
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#define PWRR_RDPD_SHIFT 0
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#define PWRR_RDAG_SHIFT 1
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#define PWRR_RDGPD_SHIFT 2
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#define PWRR_RDGPO_SHIFT 3
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#define PWRR_RDPD (1 << PWRR_RDPD_SHIFT)
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#define PWRR_RDAG (1 << PWRR_RDAG_SHIFT)
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#define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT)
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#define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT)
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#define PWRR_RDPD (1 << PWRR_RDPD_SHIFT)
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#define PWRR_RDAG (1 << PWRR_RDAG_SHIFT)
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#define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT)
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#define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT)
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/*
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* Values to write to GICR_PWRR register to power redistributor
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* for operating through the core (GICR_PWRR.RDAG = 0)
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*/
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#define PWRR_ON (0 << PWRR_RDPD_SHIFT)
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#define PWRR_OFF (1 << PWRR_RDPD_SHIFT)
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#define PWRR_ON (0 << PWRR_RDPD_SHIFT)
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#define PWRR_OFF (1 << PWRR_RDPD_SHIFT)
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#if GICV3_SUPPORT_GIC600
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@ -115,7 +117,8 @@ static bool gicv3_is_gic600(uintptr_t gicr_base)
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{
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uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR);
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return (reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600;
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return (((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) ||
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((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600AE));
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}
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#endif
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