feat(ls1088a): add new SoC platform ls1088a
LS1088A is a cost-effective, powerefficient, and highly integrated SoC device featuring eight extremely power-efficient 64-bit ARM Cortex-A53 cores with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.6 GHz. This patch is to add ls1088a SoC support in TF-A. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Id9ebcdad1beab07ea81a41955edd4f471d6cf090
This commit is contained in:
Jiafei Pan
parent
ccb71e33eb
commit
9df5ba05b4
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@ -182,7 +182,7 @@ void ls_bl2_el3_plat_arch_setup(void)
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unsigned int flags = 0U;
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/* Initialise the IO layer and register platform IO devices */
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ls_setup_page_tables(
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#if SEPARATE_RW_AND_NOLOAD
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#if SEPARATE_BL2_NOLOAD_REGION
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BL2_START,
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BL2_LIMIT - BL2_START,
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#else
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,69 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl plat_reset_handler
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.globl platform_mem_init
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func platform_mem1_init
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ret
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endfunc platform_mem1_init
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func apply_platform_errata
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ret
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endfunc apply_platform_errata
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func plat_reset_handler
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mov x29, x30
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bl apply_platform_errata
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#if defined(IMAGE_BL31)
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ldr x0, =POLICY_SMMU_PAGESZ_64K
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cbz x0, 1f
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/* Set the SMMU page size in the sACR register */
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bl _set_smmu_pagesz_64
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#endif
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1:
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mov x30, x29
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ret
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endfunc plat_reset_handler
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/*
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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*/
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func plat_secondary_cold_boot_setup
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/* ls1088a does not do cold boot for secondary CPU */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/*
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, 0x0
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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@ -0,0 +1,229 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include "dcfg_lsch3.h"
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#include "soc_default_base_addr.h"
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#include "soc_default_helper_macros.h"
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/*
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* SVR Definition of LS1088A
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* A: without security
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* AE: with security
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* (not include major and minor rev)
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*/
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#define SVR_LS1044A 0x870323
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#define SVR_LS1044AE 0x870322
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#define SVR_LS1048A 0x870321
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#define SVR_LS1048AE 0x870320
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#define SVR_LS1084A 0x870303
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#define SVR_LS1084AE 0x870302
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#define SVR_LS1088A 0x870301
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#define SVR_LS1088AE 0x870300
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#define SVR_WO_E 0xFFFFFE
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/* Number of cores in platform */
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#define NUMBER_OF_CLUSTERS 2
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#define CORES_PER_CLUSTER 4
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#define PLATFORM_CORE_COUNT (NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER)
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/* set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS 1
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#define NUM_DRAM_REGIONS 2
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#define NXP_DRAM0_ADDR 0x80000000
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#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
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#define NXP_DRAM1_ADDR 0x8080000000
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#define NXP_DRAM1_MAX_SIZE 0x7F80000000 /* 510 G */
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/* DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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#define NXP_POWMGTDCR 0x700123C20
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/* epu register offsets and values */
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#define EPU_EPGCR_OFFSET 0x0
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#define EPU_EPIMCR10_OFFSET 0x128
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#define EPU_EPCTR10_OFFSET 0xa28
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#define EPU_EPCCR10_OFFSET 0x828
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#ifdef EPU_EPCCR10_VAL
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#undef EPU_EPCCR10_VAL
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#endif
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#define EPU_EPCCR10_VAL 0xf2800000
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#define EPU_EPIMCR10_VAL 0xba000000
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#define EPU_EPCTR10_VAL 0x0
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#define EPU_EPGCR_VAL (1 << 31)
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/* pmu register offsets and values */
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#define PMU_PCPW20SR_OFFSET 0x830
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#define PMU_CLAINACTSETR_OFFSET 0x1100
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#define PMU_CLAINACTCLRR_OFFSET 0x1104
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#define PMU_CLSINACTSETR_OFFSET 0x1108
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#define PMU_CLSINACTCLRR_OFFSET 0x110C
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#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
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#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114
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#define PMU_CLL2FLUSHSR_OFFSET 0x1118
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#define PMU_POWMGTCSR_OFFSET 0x4000
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#define PMU_IPPDEXPCR0_OFFSET 0x4040
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#define PMU_IPPDEXPCR1_OFFSET 0x4044
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#define PMU_IPPDEXPCR2_OFFSET 0x4048
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#define PMU_IPPDEXPCR3_OFFSET 0x404C
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#define PMU_IPPDEXPCR4_OFFSET 0x4050
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#define PMU_IPPDEXPCR5_OFFSET 0x4054
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#define PMU_IPSTPCR0_OFFSET 0x4120
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#define PMU_IPSTPCR1_OFFSET 0x4124
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#define PMU_IPSTPCR2_OFFSET 0x4128
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#define PMU_IPSTPCR3_OFFSET 0x412C
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#define PMU_IPSTPCR4_OFFSET 0x4130
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#define PMU_IPSTPCR5_OFFSET 0x4134
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#define PMU_IPSTPCR6_OFFSET 0x4138
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#define PMU_IPSTPACK0_OFFSET 0x4140
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#define PMU_IPSTPACK1_OFFSET 0x4144
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#define PMU_IPSTPACK2_OFFSET 0x4148
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#define PMU_IPSTPACK3_OFFSET 0x414C
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#define PMU_IPSTPACK4_OFFSET 0x4150
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#define PMU_IPSTPACK5_OFFSET 0x4154
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#define PMU_IPSTPACK6_OFFSET 0x4158
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#define PMU_POWMGTCSR_VAL (1 << 20)
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#define IPPDEXPCR0_MASK 0xFFFFFFFF
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#define IPPDEXPCR1_MASK 0xFFFFFFFF
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#define IPPDEXPCR2_MASK 0xFFFFFFFF
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#define IPPDEXPCR3_MASK 0xFFFFFFFF
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#define IPPDEXPCR4_MASK 0xFFFFFFFF
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#define IPPDEXPCR5_MASK 0xFFFFFFFF
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/* DEVDISR5_FLX_TMR */
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#define IPPDEXPCR_FLX_TMR 0x00004000
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#define DEVDISR5_FLX_TMR 0x00004000
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#define IPSTPCR0_VALUE 0x0041310C
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#define IPSTPCR1_VALUE 0x000003FF
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#define IPSTPCR2_VALUE 0x00013006
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/* Dont' stop UART */
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#define IPSTPCR3_VALUE 0x0000033A
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#define IPSTPCR4_VALUE 0x00103300
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#define IPSTPCR5_VALUE 0x00000001
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#define IPSTPCR6_VALUE 0x00000000
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#define TZPC_BLOCK_SIZE 0x1000
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/* PORSR1 */
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#define PORSR1_RCW_MASK 0xFF800000
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#define PORSR1_RCW_SHIFT 23
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/* CFG_RCW_SRC[6:0] */
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#define RCW_SRC_TYPE_MASK 0x70
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/* RCW SRC NOR */
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#define NOR_16B_VAL 0x20
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/*
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* RCW SRC Serial Flash
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* 1. SERAIL NOR (QSPI)
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* 2. OTHERS (SD/MMC, SPI, I2C1)
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*/
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#define RCW_SRC_SERIAL_MASK 0x7F
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#define QSPI_VAL 0x62
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#define SDHC_VAL 0x40
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#define EMMC_VAL 0x41
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/*
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* Required LS standard platform porting definitions
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* for CCN-504 - Read from RN-F node ID register
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*/
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#define PLAT_CLUSTER_TO_CCN_ID_MAP 1, 9, 11, 19
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
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/*
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* Clock Divisors
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*/
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#define NXP_PLATFORM_CLK_DIVIDER 1
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#define NXP_UART_CLK_DIVIDER 2
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/* dcfg register offsets and values */
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#define DCFG_DEVDISR1_OFFSET 0x70
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#define DCFG_DEVDISR2_OFFSET 0x74
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#define DCFG_DEVDISR3_OFFSET 0x78
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#define DCFG_DEVDISR5_OFFSET 0x80
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#define DCFG_DEVDISR6_OFFSET 0x84
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#define DCFG_DEVDISR1_SEC (1 << 22)
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#define DCFG_DEVDISR3_QBMAIN (1 << 12)
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#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
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#define DCFG_DEVDISR5_MEM (1 << 0)
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#define DEVDISR1_VALUE 0x0041310c
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#define DEVDISR2_VALUE 0x000003ff
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#define DEVDISR3_VALUE 0x00013006
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#define DEVDISR4_VALUE 0x0000033e
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#define DEVDISR5_VALUE 0x00103300
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#define DEVDISR6_VALUE 0x00000001
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/*
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* pwr mgmt features supported in the soc-specific code:
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* value == 0x0, the soc code does not support this feature
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* value != 0x0, the soc code supports this feature
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*/
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#define SOC_CORE_RELEASE 0x1
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#define SOC_CORE_RESTART 0x1
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#define SOC_CORE_OFF 0x1
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#define SOC_CORE_STANDBY 0x1
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#define SOC_CORE_PWR_DWN 0x1
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#define SOC_CLUSTER_STANDBY 0x1
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#define SOC_CLUSTER_PWR_DWN 0x1
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#define SOC_SYSTEM_STANDBY 0x1
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#define SOC_SYSTEM_PWR_DWN 0x1
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#define SOC_SYSTEM_OFF 0x1
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#define SOC_SYSTEM_RESET 0x1
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#define SYSTEM_PWR_DOMAINS 1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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NUMBER_OF_CLUSTERS + \
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SYSTEM_PWR_DOMAINS)
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/* Power state coordination occurs at the system level */
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#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
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/* Local power state for power domains in Run state */
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#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
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/* define retention state */
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
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#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
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/* define power-down state */
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
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#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
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#ifndef __ASSEMBLER__
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/* CCI slave interfaces */
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static const int cci_map[] = {
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3,
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4,
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};
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void soc_init_lowlevel(void);
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void soc_init_percpu(void);
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void _soc_set_start_addr(unsigned long addr);
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void _set_platform_security(void);
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#endif
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#endif /* SOC_H */
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@ -0,0 +1,397 @@
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/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch.h>
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#include <caam.h>
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#include <cci.h>
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#include <common/debug.h>
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#include <dcfg.h>
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#ifdef I2C_INIT
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#include <i2c.h>
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#endif
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <ls_interconnect.h>
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#if TRUSTED_BOARD_BOOT
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#include <nxp_smmu.h>
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#endif
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#include <nxp_timer.h>
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#include <plat_console.h>
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#include <plat_gic.h>
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#include <plat_tzc400.h>
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#include <pmu.h>
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#if defined(NXP_SFP_ENABLED)
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#include <sfp.h>
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#endif
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#include <errata.h>
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#ifdef CONFIG_OCRAM_ECC_EN
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#include <ocram.h>
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#endif
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#include <plat_common.h>
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#include <platform_def.h>
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#include <soc.h>
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static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2];
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static struct soc_type soc_list[] = {
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SOC_ENTRY(LS1044A, LS1044A, 1, 4),
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SOC_ENTRY(LS1044AE, LS1044AE, 1, 4),
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SOC_ENTRY(LS1048A, LS1048A, 1, 4),
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SOC_ENTRY(LS1048AE, LS1048AE, 1, 4),
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SOC_ENTRY(LS1084A, LS1084A, 2, 4),
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SOC_ENTRY(LS1084AE, LS1084AE, 2, 4),
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SOC_ENTRY(LS1088A, LS1088A, 2, 4),
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SOC_ENTRY(LS1088AE, LS1088AE, 2, 4),
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};
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static dcfg_init_info_t dcfg_init_data = {
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.g_nxp_dcfg_addr = NXP_DCFG_ADDR,
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.nxp_sysclk_freq = NXP_SYSCLK_FREQ,
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.nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
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.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
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};
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/*
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* This function dynamically constructs the topology according to
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* SoC Flavor and returns it.
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*/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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unsigned int i;
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uint8_t num_clusters, cores_per_cluster;
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get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
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/*
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* The highest level is the system level. The next level is constituted
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* by clusters and then cores in clusters.
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*/
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_power_domain_tree_desc[0] = 1;
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_power_domain_tree_desc[1] = num_clusters;
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for (i = 0; i < _power_domain_tree_desc[1]; i++) {
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_power_domain_tree_desc[i + 2] = cores_per_cluster;
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}
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return _power_domain_tree_desc;
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}
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CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
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assert_invalid_ls1088a_cluster_count);
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/*
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* This function returns the core count within the cluster corresponding to
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* `mpidr`.
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*/
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unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
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{
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return CORES_PER_CLUSTER;
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}
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/*
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* This function returns the total number of cores in the SoC
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*/
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unsigned int get_tot_num_cores(void)
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{
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uint8_t num_clusters, cores_per_cluster;
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get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
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return (num_clusters * cores_per_cluster);
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}
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/*
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* This function returns the PMU IDLE Cluster mask.
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*/
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unsigned int get_pmu_idle_cluster_mask(void)
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{
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uint8_t num_clusters, cores_per_cluster;
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get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
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return ((1 << num_clusters) - 2);
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}
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/*
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* This function returns the PMU Flush Cluster mask.
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*/
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unsigned int get_pmu_flush_cluster_mask(void)
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{
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uint8_t num_clusters, cores_per_cluster;
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get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
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return ((1 << num_clusters) - 2);
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}
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/*
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||||
* This function returns the PMU IDLE Core mask.
|
||||
*/
|
||||
unsigned int get_pmu_idle_core_mask(void)
|
||||
{
|
||||
return ((1 << get_tot_num_cores()) - 2);
|
||||
}
|
||||
|
||||
#ifdef IMAGE_BL2
|
||||
|
||||
void soc_bl2_prepare_exit(void)
|
||||
{
|
||||
#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
|
||||
set_sfp_wr_disable();
|
||||
#endif
|
||||
}
|
||||
|
||||
void soc_preload_setup(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the boot device based on RCW_SRC
|
||||
*/
|
||||
enum boot_device get_boot_dev(void)
|
||||
{
|
||||
enum boot_device src = BOOT_DEVICE_NONE;
|
||||
uint32_t porsr1;
|
||||
uint32_t rcw_src, val;
|
||||
|
||||
porsr1 = read_reg_porsr1();
|
||||
|
||||
rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
|
||||
|
||||
/* RCW SRC NOR */
|
||||
val = rcw_src & RCW_SRC_TYPE_MASK;
|
||||
if (val == NOR_16B_VAL) {
|
||||
src = BOOT_DEVICE_IFC_NOR;
|
||||
INFO("RCW BOOT SRC is IFC NOR\n");
|
||||
} else {
|
||||
val = rcw_src & RCW_SRC_SERIAL_MASK;
|
||||
switch (val) {
|
||||
case QSPI_VAL:
|
||||
src = BOOT_DEVICE_QSPI;
|
||||
INFO("RCW BOOT SRC is QSPI\n");
|
||||
break;
|
||||
case SDHC_VAL:
|
||||
src = BOOT_DEVICE_EMMC;
|
||||
INFO("RCW BOOT SRC is SD/EMMC\n");
|
||||
break;
|
||||
case EMMC_VAL:
|
||||
src = BOOT_DEVICE_EMMC;
|
||||
INFO("RCW BOOT SRC is SD/EMMC\n");
|
||||
break;
|
||||
default:
|
||||
src = BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
return src;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function sets up access permissions on memory regions
|
||||
*/
|
||||
void soc_mem_access(void)
|
||||
{
|
||||
dram_regions_info_t *info_dram_regions = get_dram_regions_info();
|
||||
int i = 0;
|
||||
struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
|
||||
int dram_idx, index = 1;
|
||||
|
||||
for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions;
|
||||
dram_idx++) {
|
||||
if (info_dram_regions->region[i].size == 0) {
|
||||
ERROR("DDR init failure, or");
|
||||
ERROR("DRAM regions not populated correctly.\n");
|
||||
break;
|
||||
}
|
||||
|
||||
index = populate_tzc400_reg_list(tzc400_reg_list,
|
||||
dram_idx, index,
|
||||
info_dram_regions->region[dram_idx].addr,
|
||||
info_dram_regions->region[dram_idx].size,
|
||||
NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
|
||||
}
|
||||
|
||||
mem_access_setup(NXP_TZC_ADDR, index,
|
||||
tzc400_reg_list);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function implements soc specific erratum
|
||||
* This is called before DDR is initialized or MMU is enabled
|
||||
*/
|
||||
void soc_early_init(void)
|
||||
{
|
||||
enum boot_device dev;
|
||||
dram_regions_info_t *dram_regions_info = get_dram_regions_info();
|
||||
|
||||
#ifdef CONFIG_OCRAM_ECC_EN
|
||||
ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
|
||||
#endif
|
||||
dcfg_init(&dcfg_init_data);
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
enable_timer_base_to_cluster(NXP_PMU_ADDR);
|
||||
enable_core_tb(NXP_PMU_ADDR);
|
||||
|
||||
/*
|
||||
* Use the region(NXP_SD_BLOCK_BUF_ADDR + NXP_SD_BLOCK_BUF_SIZE)
|
||||
* as dma of sd
|
||||
*/
|
||||
dev = get_boot_dev();
|
||||
if (dev == BOOT_DEVICE_EMMC) {
|
||||
mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR,
|
||||
NXP_SD_BLOCK_BUF_SIZE,
|
||||
MT_DEVICE | MT_RW | MT_NS);
|
||||
}
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
uint32_t mode;
|
||||
|
||||
sfp_init(NXP_SFP_ADDR);
|
||||
/*
|
||||
* For secure boot disable SMMU.
|
||||
* Later when platform security policy comes in picture,
|
||||
* this might get modified based on the policy
|
||||
*/
|
||||
if (check_boot_mode_secure(&mode) == true) {
|
||||
bypass_smmu(NXP_SMMU_ADDR);
|
||||
}
|
||||
|
||||
/*
|
||||
* For Mbedtls currently crypto is not supported via CAAM
|
||||
* enable it when that support is there. In tbbr.mk
|
||||
* the CAAM_INTEG is set as 0.
|
||||
*/
|
||||
#ifndef MBEDTLS_X509
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled() == false) {
|
||||
INFO("SEC is disabled.\n");
|
||||
} else {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
soc_errata();
|
||||
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
i2c_init(NXP_I2C_ADDR);
|
||||
dram_regions_info->total_dram_size = init_ddr();
|
||||
}
|
||||
#else /* !IMAGE_BL2 */
|
||||
|
||||
void soc_early_platform_setup2(void)
|
||||
{
|
||||
dcfg_init(&dcfg_init_data);
|
||||
/*
|
||||
* Initialize system level generic timer for Socs
|
||||
*/
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
}
|
||||
|
||||
void soc_platform_setup(void)
|
||||
{
|
||||
/* Initialize the GIC driver, cpu and distributor interfaces */
|
||||
static uintptr_t target_mask_array[PLATFORM_CORE_COUNT];
|
||||
static interrupt_prop_t ls_interrupt_props[] = {
|
||||
PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S),
|
||||
PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0)
|
||||
};
|
||||
|
||||
plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR,
|
||||
PLATFORM_CORE_COUNT,
|
||||
ls_interrupt_props,
|
||||
ARRAY_SIZE(ls_interrupt_props),
|
||||
target_mask_array,
|
||||
plat_core_pos);
|
||||
|
||||
plat_ls_gic_init();
|
||||
enable_init_timer();
|
||||
}
|
||||
|
||||
/*
|
||||
* This function initializes the soc from the BL31 module
|
||||
*/
|
||||
void soc_init(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
/* low-level init of the soc */
|
||||
soc_init_lowlevel();
|
||||
_init_global_data();
|
||||
soc_init_percpu();
|
||||
_initialize_psci();
|
||||
|
||||
/*
|
||||
* Initialize Interconnect for this cluster during cold boot.
|
||||
* No need for locks as no other CPU is active.
|
||||
*/
|
||||
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
|
||||
|
||||
/*
|
||||
* Enable Interconnect coherency for the primary CPU's cluster.
|
||||
*/
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
plat_ls_interconnect_enter_coherency(num_clusters);
|
||||
|
||||
/* set platform security policies */
|
||||
_set_platform_security();
|
||||
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled() == false) {
|
||||
INFO("SEC is disabled.\n");
|
||||
} else {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
}
|
||||
}
|
||||
|
||||
void soc_runtime_setup(void)
|
||||
{
|
||||
|
||||
}
|
||||
#endif /* IMAGE_BL2 */
|
||||
|
||||
/*
|
||||
* Function to return the SoC SYS CLK
|
||||
*/
|
||||
unsigned int get_sys_clk(void)
|
||||
{
|
||||
return NXP_SYSCLK_FREQ;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function returns the base counter frequency
|
||||
* after reading the first entry at CNTFID0 (0x20 offset).
|
||||
*
|
||||
* Function is used by:
|
||||
* 1. ARM common code for PSCI management.
|
||||
* 2. ARM Generic Timer init.
|
||||
*/
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
unsigned int counter_base_frequency;
|
||||
/*
|
||||
* Below register specifies the base frequency of the system counter.
|
||||
* As per NXP Board Manuals:
|
||||
* The system counter always works with SYS_REF_CLK/4 frequency clock.
|
||||
*/
|
||||
counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF);
|
||||
|
||||
return counter_base_frequency;
|
||||
}
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
#
|
||||
# Copyright 2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# This file contains the basic architecture definitions that drive the build
|
||||
#
|
||||
# -----------------------------------------------------------------------------
|
||||
|
||||
CORE_TYPE := a53
|
||||
|
||||
CACHE_LINE := 6
|
||||
|
||||
# Set to GIC400 or GIC500
|
||||
GIC := GIC500
|
||||
|
||||
# Set to CCI400 or CCN504 or CCN508
|
||||
INTERCONNECT := CCI400
|
||||
|
||||
# Select the DDR PHY generation to be used
|
||||
PLAT_DDR_PHY := PHY_GEN1
|
||||
|
||||
PHYS_SYS := 64
|
||||
|
||||
# Indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
|
||||
CHASSIS := 3
|
||||
|
||||
# TZC IP Details TZC used is TZC380 or TZC400
|
||||
TZC_ID := TZC400
|
||||
|
||||
# CONSOLE Details available is NS16550 or PL011
|
||||
CONSOLE := NS16550
|
||||
|
||||
NXP_SFP_VER := 3_4
|
||||
|
||||
# In IMAGE_BL2, compile time flag for handling Cache coherency
|
||||
# with CAAM for BL2 running from OCRAM
|
||||
SEC_MEM_NON_COHERENT := yes
|
||||
|
||||
|
||||
# OCRAM MAP for BL2
|
||||
# Before BL2
|
||||
# 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables)
|
||||
# 0x1800a000 - 0x1801Cfff -> Reserved for BL2 binary (76 KB)
|
||||
# 0x1801D000 - 0x1801ffff -> CSF header for BL2 (12 KB)
|
||||
OCRAM_START_ADDR := 0x18000000
|
||||
OCRAM_SIZE := 0x20000
|
||||
|
||||
CSF_HDR_SZ := 0x3000
|
||||
|
||||
# Area of OCRAM reserved by ROM code
|
||||
NXP_ROM_RSVD := 0xa000
|
||||
|
||||
# Input to CST create_hdr_isbc tool
|
||||
BL2_HDR_LOC := 0x1801D000
|
||||
|
||||
# Location of BL2 on OCRAM
|
||||
# BL2_BASE=OCRAM_START_ADDR+NXP_ROM_RSVD
|
||||
BL2_BASE := 0x1800a000
|
||||
|
||||
# SoC ERRATUM to be enabled
|
||||
ERRATA_SOC_A008850 := 1
|
||||
|
||||
# ARM Erratum
|
||||
ERRATA_A53_855873 := 1
|
||||
|
||||
# DDR Erratum
|
||||
ERRATA_DDR_A008511 := 1
|
||||
ERRATA_DDR_A009803 := 1
|
||||
ERRATA_DDR_A009942 := 1
|
||||
ERRATA_DDR_A010165 := 1
|
||||
|
||||
# Define Endianness of each module
|
||||
NXP_ESDHC_ENDIANNESS := LE
|
||||
NXP_SFP_ENDIANNESS := LE
|
||||
NXP_GPIO_ENDIANNESS := LE
|
||||
NXP_SNVS_ENDIANNESS := LE
|
||||
NXP_GUR_ENDIANNESS := LE
|
||||
NXP_SEC_ENDIANNESS := LE
|
||||
NXP_DDR_ENDIANNESS := LE
|
||||
NXP_QSPI_ENDIANNESS := LE
|
||||
|
||||
# OCRAM ECC Enabled
|
||||
OCRAM_ECC_EN := yes
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
#
|
||||
# Copyright 2022 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# SoC-specific build parameters
|
||||
SOC := ls1088a
|
||||
PLAT_PATH := plat/nxp
|
||||
PLAT_COMMON_PATH:= plat/nxp/common
|
||||
PLAT_DRIVERS_PATH:= drivers/nxp
|
||||
PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC}
|
||||
BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD}
|
||||
|
||||
# Separate BL2 NOLOAD region (.bss, stack, page tables). need to
|
||||
# define BL2_NOLOAD_START and BL2_NOLOAD_LIMIT
|
||||
SEPARATE_BL2_NOLOAD_REGION := 1
|
||||
|
||||
# get SoC-specific defnitions
|
||||
include ${PLAT_SOC_PATH}/soc.def
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
|
||||
|
||||
# For Security Features
|
||||
DISABLE_FUSE_WRITE := 1
|
||||
ifeq (${TRUSTED_BOARD_BOOT}, 1)
|
||||
ifeq (${GENERATE_COT},1)
|
||||
# Save Keys to be used by DDR FIP image
|
||||
SAVE_KEYS=1
|
||||
endif
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
|
||||
# Used by create_pbl tool to
|
||||
# create bl2_<boot_mode>_sec.pbl image
|
||||
SECURE_BOOT := yes
|
||||
endif
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
|
||||
|
||||
# Selecting Drivers for SoC
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
|
||||
|
||||
# Selecting PSCI & SIP_SVC support
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
|
||||
|
||||
|
||||
# Adding SoC specific files
|
||||
include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
|
||||
|
||||
PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
|
||||
-I${BOARD_PATH}\
|
||||
-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
|
||||
-I${PLAT_COMMON_PATH}/soc_errata\
|
||||
-I${PLAT_COMMON_PATH}/include\
|
||||
-I${PLAT_SOC_PATH}/include
|
||||
|
||||
ifeq (${SECURE_BOOT},yes)
|
||||
include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
|
||||
endif
|
||||
|
||||
ifeq (${PSCI_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/psci/psci.mk
|
||||
endif
|
||||
|
||||
ifeq (${SIPSVC_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
|
||||
endif
|
||||
|
||||
# for fuse-fip & fuse-programming
|
||||
ifeq (${FUSE_PROG}, 1)
|
||||
include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
|
||||
endif
|
||||
|
||||
ifeq (${IMG_LOADR_NEEDED},yes)
|
||||
include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
|
||||
endif
|
||||
|
||||
# Adding source files for the above selected drivers.
|
||||
include ${PLAT_DRIVERS_PATH}/drivers.mk
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
|
||||
${PLAT_SOC_PATH}/${ARCH}/${SOC}_helpers.S\
|
||||
${PLAT_SOC_PATH}/soc.c
|
||||
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
|
||||
${PSCI_SOURCES}\
|
||||
${SIPSVC_SOURCES}\
|
||||
${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
|
||||
|
||||
ifeq (${TEST_BL31}, 1)
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S \
|
||||
${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
|
||||
endif
|
||||
|
||||
BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
|
||||
${TBBR_SOURCES}\
|
||||
${FUSE_SOURCES}
|
||||
|
||||
# Adding TFA setup files
|
||||
include ${PLAT_PATH}/common/setup/common.mk
|
||||
Loading…
Reference in New Issue