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Tegra186: Update API for reset vector ARI 

The TEGRA_ARI_COPY_MISCREG_AA64_RST ARI should be called with
request_lo/hi set to zero. MTS automatically takes the reset
vector from MISCREG_AA64_RST register and does not need it to
be passed as parameters.  This patch updates the API and the
caller function accordingly.

Change-Id: Ie3e3402d93951102239d988ca9f0cdf94f290d2f
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Krishna Sitaraman 2016-09-02 16:53:04 -07:00 committed by Varun Wadekar
parent 322b00fcfb
commit a259293ebe
4 changed files with 8 additions and 10 deletions
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8
plat/nvidia/tegra/soc/t186/drivers/include/mce.h
View File

@ -338,9 +338,7 @@ typedef struct arch_mce_ops {
* This ARI request allows updating the reset vector register for
* D15 and A57 CPUs.
*/
int (*update_reset_vector)(uint32_t ari_base,
uint32_t addr_low,
uint32_t addr_high);
int (*update_reset_vector)(uint32_t ari_base);
/*
* This ARI request instructs the ROC to flush A57 data caches in
* order to maintain coherency with the Denver cluster.
@ -397,7 +395,7 @@ typedef struct arch_mce_ops {
int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
uint64_t arg2);
int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi);
int mce_update_reset_vector(void);
int mce_update_gsc_videomem(void);
int mce_update_gsc_tzdram(void);
int mce_update_gsc_tzram(void);
@ -418,7 +416,7 @@ int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int ari_online_core(uint32_t ari_base, uint32_t core);
int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi);
int ari_reset_vector_update(uint32_t ari_base);
int ari_roc_flush_cache_trbits(uint32_t ari_base);
int ari_roc_flush_cache(uint32_t ari_base);
int ari_roc_clean_cache(uint32_t ari_base);

4
plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
View File

@ -334,7 +334,7 @@ int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable
return ari_request_wait(ari_base, 0, TEGRA_ARI_CC3_CTRL, val, 0);
}
int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi)
int ari_reset_vector_update(uint32_t ari_base)
{
/* clean the previous response state */
ari_clobber_response(ari_base);
@ -343,7 +343,7 @@ int ari_reset_vector_update(uint32_t ari_base, uint32_t lo, uint32_t hi)
* Need to program the CPU reset vector one time during cold boot
* and SC7 exit
*/
ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, lo, hi);
ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0, 0);
return 0;
}

4
plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
View File

@ -403,11 +403,11 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
/*******************************************************************************
* Handler to update the reset vector for CPUs
******************************************************************************/
int mce_update_reset_vector(uint32_t addr_lo, uint32_t addr_hi)
int mce_update_reset_vector(void)
{
arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
ops->update_reset_vector(mce_get_curr_cpu_ari_base(), addr_lo, addr_hi);
ops->update_reset_vector(mce_get_curr_cpu_ari_base());
return 0;
}

2
plat/nvidia/tegra/soc/t186/plat_secondary.c
View File

@ -91,5 +91,5 @@ void plat_secondary_setup(void)
addr_high);
/* update reset vector address to the CCPLEX */
mce_update_reset_vector(addr_low, addr_high);
mce_update_reset_vector();
}