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rcar_get3: drivers: ddr_b: Basic checkpatch fixes 

Do basic automated checkpatch fixes on the ddr_b, no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie401ec049a05d2c4c8044749994391adea171679
This commit is contained in:
Marek Vasut 2019-08-07 19:02:26 +02:00
parent f12039be95
commit a8497fdb72
3 changed files with 319 additions and 310 deletions
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33
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
View File

@ -255,7 +255,7 @@ static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size);
static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
static uint32_t ddrphy_regif_chk(void);
static inline void ddrphy_regif_idle();
static inline void ddrphy_regif_idle(void);
static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
uint16_t cyc);
static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
@ -297,6 +297,7 @@ struct DdrtData {
uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */
uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */
};
struct DdrtData tcal;
static void pvtcode_update(void);
@ -532,8 +533,8 @@ static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
uint32_t loop;
val = 0;
if ((PRR_PRODUCT_M3N != Prr_Product)
&& (PRR_PRODUCT_V3H != Prr_Product)) {
if ((Prr_Product != PRR_PRODUCT_M3N)
&& (Prr_Product != PRR_PRODUCT_V3H)) {
mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
dsb_sev();
@ -579,8 +580,8 @@ static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
uint32_t val;
uint32_t loop;
if ((PRR_PRODUCT_M3N != Prr_Product)
&& (PRR_PRODUCT_V3H != Prr_Product)) {
if ((Prr_Product != PRR_PRODUCT_M3N)
&& (Prr_Product != PRR_PRODUCT_V3H)) {
mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
dsb_sev();
for (loop = 0; loop < loop_max; loop++) {
@ -628,8 +629,8 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
uint32_t val;
uint32_t loop;
if ((PRR_PRODUCT_M3N != Prr_Product)
&& (PRR_PRODUCT_V3H != Prr_Product)) {
if ((Prr_Product != PRR_PRODUCT_M3N)
&& (Prr_Product != PRR_PRODUCT_V3H)) {
foreach_vch(ch) {
mmio_write_32(DBSC_DBPDRGA(ch), regadd);
dsb_sev();
@ -653,7 +654,7 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
}
}
static inline void ddrphy_regif_idle()
static inline void ddrphy_regif_idle(void)
{
uint32_t val;
@ -873,7 +874,7 @@ static uint32_t ddrphy_regif_chk(void)
ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
err = 0;
foreach_vch(ch) {
if (PI_VERSION_CODE != tmp_ach[ch])
if (tmp_ach[ch] != PI_VERSION_CODE)
err = 1;
}
return err;
@ -892,6 +893,7 @@ struct _jedec_spec1 {
uint8_t MR1;
uint8_t MR2;
};
#define JS1_USABLEC_SPEC_LO 2
#define JS1_USABLEC_SPEC_HI 5
#define JS1_FREQ_TBL_NUM 8
@ -1245,7 +1247,7 @@ static void ddrtbl_load(void)
if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
break;
}
if (JS1_USABLEC_SPEC_HI < i)
if (i > JS1_USABLEC_SPEC_HI)
js1_ind = JS1_USABLEC_SPEC_HI;
else
js1_ind = i;
@ -1624,6 +1626,7 @@ static void ddr_config_sub(void)
uint32_t tmp;
uint8_t high_byte[SLICE_CNT];
const uint32_t _par_CALVL_DEVICE_MAP = 1;
foreach_vch(ch) {
/***********************************************************************
BOARD SETTINGS (DQ,DM,VREF_DRIVING)
@ -1752,6 +1755,7 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
uint32_t slice;
uint32_t tmp;
uint32_t tgt;
if (ddr_csn / 2) {
tgt = 3;
} else {
@ -2651,6 +2655,7 @@ static uint32_t set_term_code(void)
uint32_t pvtr;
uint32_t pvtp;
uint32_t pvtn;
term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_DATA_TERM);
override = 0;
@ -2801,6 +2806,7 @@ static inline uint32_t wait_freqchgreq(uint32_t assert)
uint32_t dataL;
uint32_t count;
uint32_t ch;
count = 100000;
/* H3 Ver.1.x cannot see frqchg_req */
@ -2833,6 +2839,7 @@ static inline void set_freqchgack(uint32_t assert)
{
uint32_t ch;
uint32_t dataL;
if (assert)
dataL = 0x0CF20000;
else
@ -2845,6 +2852,7 @@ static inline void set_freqchgack(uint32_t assert)
static inline void set_dfifrequency(uint32_t freq)
{
uint32_t ch;
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
foreach_vch(ch)
mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
@ -4140,6 +4148,7 @@ static void adjust_rddqs_latency(void)
uint32_t maxlatx2;
uint32_t tmp;
uint32_t rdlat_adjx2[SLICE_CNT];
foreach_vch(ch) {
maxlatx2 = 0;
for (slice = 0; slice < SLICE_CNT; slice++) {
@ -4340,8 +4349,7 @@ int32_t rcar_dram_init(void)
ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
ddr_mul =
CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
brd_clkdiv * (brd_clkdiva + 1));
/***********************************************************************
@ -4487,6 +4495,7 @@ void pvtcode_update(void)
void pvtcode_update2(void)
{
uint32_t ch;
foreach_vch(ch) {
reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
tcal.init_cal[ch] | 0x00020000);

2
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
View File

@ -1725,7 +1725,7 @@ static uint32_t _board_judge(void)
usb2_ovc_open = opencheck_SSI_WS6();
/* RENESAS Eva-borad */
/* RENESAS Eva-board */
brd = 99;
if (Prr_Product == PRR_PRODUCT_V3H) {
/* RENESAS Condor board */