rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B
The ddr_a and ddr_b register macros are the same for the most part, unify them into a single header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I8f55d6d779837215339ac0010e8c8ab5f6748d75
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@ -5,287 +5,4 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_INIT_DRAM_REGDEF_H_
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#define BOOT_INIT_DRAM_REGDEF_H_
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/* DBSC registers */
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#define DBSC_DBSYSCONF0 0xE6790000U
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#define DBSC_DBSYSCONF1 0xE6790004U
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#define DBSC_DBPHYCONF0 0xE6790010U
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#define DBSC_DBKIND 0xE6790020U
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#define DBSC_DBMEMCONF00 0xE6790030U
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#define DBSC_DBMEMCONF01 0xE6790034U
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#define DBSC_DBMEMCONF02 0xE6790038U
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#define DBSC_DBMEMCONF03 0xE679003CU
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#define DBSC_DBMEMCONF10 0xE6790040U
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#define DBSC_DBMEMCONF11 0xE6790044U
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#define DBSC_DBMEMCONF12 0xE6790048U
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#define DBSC_DBMEMCONF13 0xE679004CU
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#define DBSC_DBMEMCONF20 0xE6790050U
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#define DBSC_DBMEMCONF21 0xE6790054U
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#define DBSC_DBMEMCONF22 0xE6790058U
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#define DBSC_DBMEMCONF23 0xE679005CU
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#define DBSC_DBMEMCONF30 0xE6790060U
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#define DBSC_DBMEMCONF31 0xE6790064U
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#define DBSC_DBMEMCONF32 0xE6790068U
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#define DBSC_DBMEMCONF33 0xE679006CU
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#define DBSC_DBSYSCNT0 0xE6790100U
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#define DBSC_DBSVCR1 0xE6790104U
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#define DBSC_DBSTATE0 0xE6790108U
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#define DBSC_DBSTATE1 0xE679010CU
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#define DBSC_DBINTEN 0xE6790180U
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#define DBSC_DBINTSTAT0 0xE6790184U
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#define DBSC_DBACEN 0xE6790200U
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#define DBSC_DBRFEN 0xE6790204U
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#define DBSC_DBCMD 0xE6790208U
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#define DBSC_DBWAIT 0xE6790210U
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#define DBSC_DBSYSCTRL0 0xE6790280U
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#define DBSC_DBTR0 0xE6790300U
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#define DBSC_DBTR1 0xE6790304U
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#define DBSC_DBTR2 0xE6790308U
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#define DBSC_DBTR3 0xE679030CU
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#define DBSC_DBTR4 0xE6790310U
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#define DBSC_DBTR5 0xE6790314U
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#define DBSC_DBTR6 0xE6790318U
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#define DBSC_DBTR7 0xE679031CU
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#define DBSC_DBTR8 0xE6790320U
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#define DBSC_DBTR9 0xE6790324U
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#define DBSC_DBTR10 0xE6790328U
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#define DBSC_DBTR11 0xE679032CU
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#define DBSC_DBTR12 0xE6790330U
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#define DBSC_DBTR13 0xE6790334U
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#define DBSC_DBTR14 0xE6790338U
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#define DBSC_DBTR15 0xE679033CU
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#define DBSC_DBTR16 0xE6790340U
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#define DBSC_DBTR17 0xE6790344U
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#define DBSC_DBTR18 0xE6790348U
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#define DBSC_DBTR19 0xE679034CU
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#define DBSC_DBTR20 0xE6790350U
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#define DBSC_DBTR21 0xE6790354U
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#define DBSC_DBTR22 0xE6790358U
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#define DBSC_DBTR23 0xE679035CU
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#define DBSC_DBTR24 0xE6790360U
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#define DBSC_DBTR25 0xE6790364U
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#define DBSC_DBBL 0xE6790400U
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#define DBSC_DBRFCNF1 0xE6790414U
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#define DBSC_DBRFCNF2 0xE6790418U
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#define DBSC_DBTSPCNF 0xE6790420U
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#define DBSC_DBCALCNF 0xE6790424U
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#define DBSC_DBRNK2 0xE6790438U
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#define DBSC_DBRNK3 0xE679043CU
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#define DBSC_DBRNK4 0xE6790440U
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#define DBSC_DBRNK5 0xE6790444U
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#define DBSC_DBPDNCNF 0xE6790450U
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#define DBSC_DBODT0 0xE6790460U
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#define DBSC_DBODT1 0xE6790464U
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#define DBSC_DBODT2 0xE6790468U
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#define DBSC_DBODT3 0xE679046CU
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#define DBSC_DBODT4 0xE6790470U
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#define DBSC_DBODT5 0xE6790474U
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#define DBSC_DBODT6 0xE6790478U
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#define DBSC_DBODT7 0xE679047CU
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#define DBSC_DBADJ0 0xE6790500U
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#define DBSC_DBDBICNT 0xE6790518U
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#define DBSC_DBDFIPMSTRCNF 0xE6790520U
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#define DBSC_DBDFIPMSTRSTAT 0xE6790524U
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#define DBSC_DBDFILPCNF 0xE6790528U
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#define DBSC_DBDFICUPDCNF 0xE679052CU
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#define DBSC_DBDFISTAT0 0xE6790600U
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#define DBSC_DBDFICNT0 0xE6790604U
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#define DBSC_DBPDCNT00 0xE6790610U
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#define DBSC_DBPDCNT01 0xE6790614U
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#define DBSC_DBPDCNT02 0xE6790618U
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#define DBSC_DBPDCNT03 0xE679061CU
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#define DBSC_DBPDLK0 0xE6790620U
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#define DBSC_DBPDRGA0 0xE6790624U
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#define DBSC_DBPDRGD0 0xE6790628U
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#define DBSC_DBPDSTAT00 0xE6790630U
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#define DBSC_DBDFISTAT1 0xE6790640U
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#define DBSC_DBDFICNT1 0xE6790644U
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#define DBSC_DBPDCNT10 0xE6790650U
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#define DBSC_DBPDCNT11 0xE6790654U
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#define DBSC_DBPDCNT12 0xE6790658U
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#define DBSC_DBPDCNT13 0xE679065CU
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#define DBSC_DBPDLK1 0xE6790660U
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#define DBSC_DBPDRGA1 0xE6790664U
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#define DBSC_DBPDRGD1 0xE6790668U
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#define DBSC_DBPDSTAT10 0xE6790670U
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#define DBSC_DBDFISTAT2 0xE6790680U
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#define DBSC_DBDFICNT2 0xE6790684U
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#define DBSC_DBPDCNT20 0xE6790690U
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#define DBSC_DBPDCNT21 0xE6790694U
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#define DBSC_DBPDCNT22 0xE6790698U
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#define DBSC_DBPDCNT23 0xE679069CU
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#define DBSC_DBPDLK2 0xE67906A0U
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#define DBSC_DBPDRGA2 0xE67906A4U
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#define DBSC_DBPDRGD2 0xE67906A8U
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#define DBSC_DBPDSTAT20 0xE67906B0U
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#define DBSC_DBDFISTAT3 0xE67906C0U
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#define DBSC_DBDFICNT3 0xE67906C4U
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#define DBSC_DBPDCNT30 0xE67906D0U
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#define DBSC_DBPDCNT31 0xE67906D4U
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#define DBSC_DBPDCNT32 0xE67906D8U
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#define DBSC_DBPDCNT33 0xE67906DCU
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#define DBSC_DBPDLK3 0xE67906E0U
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#define DBSC_DBPDRGA3 0xE67906E4U
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#define DBSC_DBPDRGD3 0xE67906E8U
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#define DBSC_DBPDSTAT30 0xE67906F0U
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#define DBSC_DBBUS0CNF0 0xE6790800U
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#define DBSC_DBBUS0CNF1 0xE6790804U
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#define DBSC_DBCAM0CNF1 0xE6790904U
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#define DBSC_DBCAM0CNF2 0xE6790908U
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#define DBSC_DBCAM0CNF3 0xE679090CU
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#define DBSC_DBCAM0CTRL0 0xE6790940U
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#define DBSC_DBCAM0STAT0 0xE6790980U
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#define DBSC_DBCAM1STAT0 0xE6790990U
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#define DBSC_DBBCAMSWAP 0xE67909F0U
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#define DBSC_DBBCAMDIS 0xE67909FCU
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#define DBSC_DBSCHCNT0 0xE6791000U
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#define DBSC_DBSCHCNT1 0xE6791004U
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#define DBSC_DBSCHSZ0 0xE6791010U
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#define DBSC_DBSCHRW0 0xE6791020U
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#define DBSC_DBSCHRW1 0xE6791024U
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#define DBSC_DBSCHQOS00 0xE6791030U
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#define DBSC_DBSCHQOS01 0xE6791034U
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#define DBSC_DBSCHQOS02 0xE6791038U
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#define DBSC_DBSCHQOS03 0xE679103CU
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#define DBSC_DBSCHQOS10 0xE6791040U
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#define DBSC_DBSCHQOS11 0xE6791044U
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#define DBSC_DBSCHQOS12 0xE6791048U
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#define DBSC_DBSCHQOS13 0xE679104CU
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#define DBSC_DBSCHQOS20 0xE6791050U
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#define DBSC_DBSCHQOS21 0xE6791054U
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#define DBSC_DBSCHQOS22 0xE6791058U
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#define DBSC_DBSCHQOS23 0xE679105CU
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#define DBSC_DBSCHQOS30 0xE6791060U
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#define DBSC_DBSCHQOS31 0xE6791064U
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#define DBSC_DBSCHQOS32 0xE6791068U
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#define DBSC_DBSCHQOS33 0xE679106CU
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#define DBSC_DBSCHQOS40 0xE6791070U
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#define DBSC_DBSCHQOS41 0xE6791074U
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#define DBSC_DBSCHQOS42 0xE6791078U
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#define DBSC_DBSCHQOS43 0xE679107CU
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#define DBSC_DBSCHQOS50 0xE6791080U
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#define DBSC_DBSCHQOS51 0xE6791084U
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#define DBSC_DBSCHQOS52 0xE6791088U
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#define DBSC_DBSCHQOS53 0xE679108CU
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#define DBSC_DBSCHQOS60 0xE6791090U
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#define DBSC_DBSCHQOS61 0xE6791094U
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#define DBSC_DBSCHQOS62 0xE6791098U
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#define DBSC_DBSCHQOS63 0xE679109CU
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#define DBSC_DBSCHQOS70 0xE67910A0U
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#define DBSC_DBSCHQOS71 0xE67910A4U
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#define DBSC_DBSCHQOS72 0xE67910A8U
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#define DBSC_DBSCHQOS73 0xE67910ACU
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#define DBSC_DBSCHQOS80 0xE67910B0U
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#define DBSC_DBSCHQOS81 0xE67910B4U
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#define DBSC_DBSCHQOS82 0xE67910B8U
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#define DBSC_DBSCHQOS83 0xE67910BCU
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#define DBSC_DBSCHQOS90 0xE67910C0U
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#define DBSC_DBSCHQOS91 0xE67910C4U
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#define DBSC_DBSCHQOS92 0xE67910C8U
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#define DBSC_DBSCHQOS93 0xE67910CCU
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#define DBSC_DBSCHQOS100 0xE67910D0U
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#define DBSC_DBSCHQOS101 0xE67910D4U
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#define DBSC_DBSCHQOS102 0xE67910D8U
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#define DBSC_DBSCHQOS103 0xE67910DCU
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#define DBSC_DBSCHQOS110 0xE67910E0U
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#define DBSC_DBSCHQOS111 0xE67910E4U
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#define DBSC_DBSCHQOS112 0xE67910E8U
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#define DBSC_DBSCHQOS113 0xE67910ECU
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#define DBSC_DBSCHQOS120 0xE67910F0U
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#define DBSC_DBSCHQOS121 0xE67910F4U
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#define DBSC_DBSCHQOS122 0xE67910F8U
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#define DBSC_DBSCHQOS123 0xE67910FCU
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#define DBSC_DBSCHQOS130 0xE6791100U
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#define DBSC_DBSCHQOS131 0xE6791104U
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#define DBSC_DBSCHQOS132 0xE6791108U
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#define DBSC_DBSCHQOS133 0xE679110CU
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#define DBSC_DBSCHQOS140 0xE6791110U
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#define DBSC_DBSCHQOS141 0xE6791114U
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#define DBSC_DBSCHQOS142 0xE6791118U
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#define DBSC_DBSCHQOS143 0xE679111CU
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#define DBSC_DBSCHQOS150 0xE6791120U
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#define DBSC_DBSCHQOS151 0xE6791124U
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#define DBSC_DBSCHQOS152 0xE6791128U
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#define DBSC_DBSCHQOS153 0xE679112CU
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#define DBSC_SCFCTST0 0xE6791700U
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#define DBSC_SCFCTST1 0xE6791708U
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#define DBSC_SCFCTST2 0xE679170CU
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#define DBSC_DBMRRDR0 0xE6791800U
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#define DBSC_DBMRRDR1 0xE6791804U
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#define DBSC_DBMRRDR2 0xE6791808U
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#define DBSC_DBMRRDR3 0xE679180CU
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#define DBSC_DBMRRDR4 0xE6791810U
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#define DBSC_DBMRRDR5 0xE6791814U
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#define DBSC_DBMRRDR6 0xE6791818U
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#define DBSC_DBMRRDR7 0xE679181CU
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#define DBSC_DBDTMP0 0xE6791820U
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#define DBSC_DBDTMP1 0xE6791824U
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#define DBSC_DBDTMP2 0xE6791828U
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#define DBSC_DBDTMP3 0xE679182CU
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#define DBSC_DBDTMP4 0xE6791830U
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#define DBSC_DBDTMP5 0xE6791834U
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#define DBSC_DBDTMP6 0xE6791838U
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#define DBSC_DBDTMP7 0xE679183CU
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#define DBSC_DBDQSOSC00 0xE6791840U
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#define DBSC_DBDQSOSC01 0xE6791844U
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#define DBSC_DBDQSOSC10 0xE6791848U
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#define DBSC_DBDQSOSC11 0xE679184CU
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#define DBSC_DBDQSOSC20 0xE6791850U
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#define DBSC_DBDQSOSC21 0xE6791854U
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#define DBSC_DBDQSOSC30 0xE6791858U
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#define DBSC_DBDQSOSC31 0xE679185CU
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#define DBSC_DBDQSOSC40 0xE6791860U
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#define DBSC_DBDQSOSC41 0xE6791864U
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#define DBSC_DBDQSOSC50 0xE6791868U
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#define DBSC_DBDQSOSC51 0xE679186CU
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#define DBSC_DBDQSOSC60 0xE6791870U
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#define DBSC_DBDQSOSC61 0xE6791874U
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#define DBSC_DBDQSOSC70 0xE6791878U
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#define DBSC_DBDQSOSC71 0xE679187CU
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#define DBSC_DBOSCTHH00 0xE6791880U
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#define DBSC_DBOSCTHH01 0xE6791884U
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#define DBSC_DBOSCTHH10 0xE6791888U
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#define DBSC_DBOSCTHH11 0xE679188CU
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#define DBSC_DBOSCTHH20 0xE6791890U
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#define DBSC_DBOSCTHH21 0xE6791894U
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#define DBSC_DBOSCTHH30 0xE6791898U
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#define DBSC_DBOSCTHH31 0xE679189CU
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#define DBSC_DBOSCTHH40 0xE67918A0U
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#define DBSC_DBOSCTHH41 0xE67918A4U
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#define DBSC_DBOSCTHH50 0xE67918A8U
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#define DBSC_DBOSCTHH51 0xE67918ACU
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#define DBSC_DBOSCTHH60 0xE67918B0U
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#define DBSC_DBOSCTHH61 0xE67918B4U
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#define DBSC_DBOSCTHH70 0xE67918B8U
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#define DBSC_DBOSCTHH71 0xE67918BCU
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#define DBSC_DBOSCTHL00 0xE67918C0U
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#define DBSC_DBOSCTHL01 0xE67918C4U
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#define DBSC_DBOSCTHL10 0xE67918C8U
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#define DBSC_DBOSCTHL11 0xE67918CCU
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#define DBSC_DBOSCTHL20 0xE67918D0U
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#define DBSC_DBOSCTHL21 0xE67918D4U
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#define DBSC_DBOSCTHL30 0xE67918D8U
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#define DBSC_DBOSCTHL31 0xE67918DCU
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#define DBSC_DBOSCTHL40 0xE67918E0U
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#define DBSC_DBOSCTHL41 0xE67918E4U
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#define DBSC_DBOSCTHL50 0xE67918E8U
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#define DBSC_DBOSCTHL51 0xE67918ECU
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#define DBSC_DBOSCTHL60 0xE67918F0U
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#define DBSC_DBOSCTHL61 0xE67918F4U
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#define DBSC_DBOSCTHL70 0xE67918F8U
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#define DBSC_DBOSCTHL71 0xE67918FCU
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#define DBSC_DBMEMSWAPCONF0 0xE6792000U
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/* CPG registers */
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#define CPG_SRCR4 0xE61500BCU
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#define CPG_PLLECR 0xE61500D0U
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#define CPG_CPGWPR 0xE6150900U
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#define CPG_CPGWPCR 0xE6150904U
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#define CPG_SRSTCLR4 0xE6150950U
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/* MODE Monitor registers */
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#define RST_MODEMR 0xE6160060U
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#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
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#include "../ddr_regs.h"
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@ -8,8 +8,8 @@
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#include <stdint.h>
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#include <lib/mmio.h>
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#include <common/debug.h>
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#include "boot_init_dram_regdef.h"
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#include "rcar_def.h"
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#include "../ddr_regs.h"
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#define RCAR_DDR_VERSION "rev.0.01"
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@ -23,7 +23,7 @@ static void init_ddr_d3_1866(void)
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mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
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mmio_write_32(DBSC_DBKIND, 0x00000007);
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mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
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mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
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mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
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mmio_write_32(DBSC_DBTR0, 0x0000000D);
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mmio_write_32(DBSC_DBTR1, 0x00000009);
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mmio_write_32(DBSC_DBODT0, 0x00000001);
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mmio_write_32(DBSC_DBADJ0, 0x00000001);
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mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
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mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
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mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
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mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
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mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
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mmio_write_32(DBSC_SCFCTST0, 0x0D020D04);
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mmio_write_32(DBSC_SCFCTST1, 0x0306040C);
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mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
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mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
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mmio_write_32(DBSC_DBCMD, 0x01000001);
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mmio_write_32(DBSC_DBCMD, 0x08000000);
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mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
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mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
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mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058A04);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058A04);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0C058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058A00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0A206F89);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x30005E00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000F14);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x35A00D77);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2A8A2C28);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x30005E00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0014CB49);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000F14);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9;
|
||||
r3 = (r2 << 16) + (r2 << 8) + r2;
|
||||
r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000011);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000012);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000016);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000017);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000019);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
|
||||
if (r6 > 0) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + (r5 << 1)) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = ((mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
r12 = (r5 >> 0x2);
|
||||
|
||||
if (r12 < r6) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + r5 +
|
||||
(r5 >> 1) + r12) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
|
||||
;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
|
||||
|
||||
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
|
||||
mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
|
||||
|
@ -302,7 +302,7 @@ static void init_ddr_d3_1866(void)
|
|||
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
|
||||
mmio_write_32(DBSC_DBRFEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBACEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
|
||||
|
||||
#ifdef ddr_qos_init_setting // only for non qos_init
|
||||
|
@ -348,7 +348,7 @@ static void init_ddr_d3_1600(void)
|
|||
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
|
||||
mmio_write_32(DBSC_DBKIND, 0x00000007);
|
||||
mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01);
|
||||
mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
|
||||
mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBTR0, 0x0000000B);
|
||||
mmio_write_32(DBSC_DBTR1, 0x00000008);
|
||||
|
@ -376,248 +376,248 @@ static void init_ddr_d3_1600(void)
|
|||
mmio_write_32(DBSC_DBODT0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBADJ0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
|
||||
mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
|
||||
mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
|
||||
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
|
||||
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
|
||||
mmio_write_32(DBSC_SCFCTST0, 0x0D020C04);
|
||||
mmio_write_32(DBSC_SCFCTST1, 0x0305040C);
|
||||
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBCMD, 0x01000001);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BBAD);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x08C05FF0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000046);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000098);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000098);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x33C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000000E);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000000E);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9;
|
||||
r3 = (r2 << 16) + (r2 << 8) + r2;
|
||||
r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000011);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000012);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000016);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000017);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000019);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000011);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000012);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r3);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000016);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000017);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000019);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r6);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
if (r6 > 0) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + (r5 << 1)) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00C0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00D8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000AF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000CF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
r12 = (r5 >> 0x2);
|
||||
|
||||
if (r12 < r6) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r6 - r12) & 0xFF));
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | (r7 & 0x7));
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + r5 +
|
||||
(r5 >> 1) + r12) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
|
||||
;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
|
||||
|
||||
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
|
||||
mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
|
||||
|
@ -626,7 +626,7 @@ static void init_ddr_d3_1600(void)
|
|||
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
|
||||
mmio_write_32(DBSC_DBRFEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBACEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
|
||||
|
||||
#ifdef ddr_qos_init_setting // only for non qos_init
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -9,7 +9,8 @@
|
|||
#include <lib/utils_def.h>
|
||||
#include <stdint.h>
|
||||
#include "boot_init_dram.h"
|
||||
#include "boot_init_dram_regdef.h"
|
||||
#include "rcar_def.h"
|
||||
#include "../ddr_regs.h"
|
||||
|
||||
static uint32_t init_ddr_v3m_1600(void)
|
||||
{
|
||||
|
@ -18,9 +19,9 @@ static uint32_t init_ddr_v3m_1600(void)
|
|||
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
|
||||
mmio_write_32(DBSC_DBKIND, 0x00000007);
|
||||
#if RCAR_DRAM_DDR3L_MEMCONF == 0
|
||||
mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); // 1GB: Eagle
|
||||
mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a02); // 1GB: Eagle
|
||||
#else
|
||||
mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); // 2GB: V3MSK
|
||||
mmio_write_32(DBSC_DBMEMCONF_0_0, 0x10030a02); // 2GB: V3MSK
|
||||
#endif
|
||||
mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBTR0, 0x0000000B);
|
||||
|
@ -79,243 +80,243 @@ static uint32_t init_ddr_v3m_1600(void)
|
|||
mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4);
|
||||
mmio_write_32(DBSC_DBSCHSZ0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBSCHRW1, 0x001a0080);
|
||||
mmio_write_32(DBSC_DBDFICNT0, 0x00000010);
|
||||
mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
|
||||
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
|
||||
mmio_write_32(DBSC_DBCMD, 0x01000001);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x80010000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058904);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000008);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000B8000);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058904);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000091);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000095);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000099);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0007BB6D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024641E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010073);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0C058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0C058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000090);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x04058900);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0780C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x08C0C170);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x30005200);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000D70);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x13C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x08C0C170);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0014A9C9);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000027);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000D70);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000004);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00000018);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00181884);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000001A);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x13C03C10);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E7);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E8);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E9);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000107);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000108);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000109);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E7);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E8);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E9);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000107);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000108);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0D0D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000109);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x000D0D0D);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010181);
|
||||
mmio_write_32(DBSC_DBCMD, 0x08000001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010601);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7;
|
||||
|
||||
if (r6 > 0) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r6);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r6);
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 | r7);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 | r7);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
(((r5 << 1) + r6) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00A0);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00A0);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010801);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00B8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000005);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0xC1AA00B8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0001F001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C000285);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x81003087);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00010401);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20);
|
||||
r6 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20);
|
||||
r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8;
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20);
|
||||
r6 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20);
|
||||
r7 = (mmio_read_32(DBSC_DBPDRGD0) & 0x7);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20);
|
||||
r7 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x7);
|
||||
r12 = (r5 >> 2);
|
||||
if (r6 - r12 > 0) {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, ((r6 - r12) & 0xFF) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, ((r6 - r12) & 0xFF) | r2);
|
||||
} else {
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, (r7 & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD0, r2 |
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, (r7 & 0x7) | r2);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, r2 |
|
||||
((r6 + r5 +
|
||||
(r5 >> 1) + r12) & 0xFF));
|
||||
}
|
||||
}
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0)))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000C0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x000000E0);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000100);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x7C0002C5);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x00015001);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000006);
|
||||
while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0)))
|
||||
;
|
||||
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30))
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000003);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0380C700);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000007);
|
||||
while (mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))
|
||||
;
|
||||
mmio_write_32(DBSC_DBPDRGA0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD0, 0x0024643E);
|
||||
mmio_write_32(DBSC_DBPDRGA_0, 0x00000021);
|
||||
mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
|
||||
|
||||
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000);
|
||||
mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001);
|
||||
|
@ -325,7 +326,7 @@ static uint32_t init_ddr_v3m_1600(void)
|
|||
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
|
||||
mmio_write_32(DBSC_DBRFEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBACEN, 0x00000001);
|
||||
mmio_write_32(DBSC_DBPDLK0, 0x00000000);
|
||||
mmio_write_32(DBSC_DBPDLK_0, 0x00000000);
|
||||
mmio_write_32(0xE67F0024, 0x00000001);
|
||||
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
|
||||
|
||||
|
|
|
@ -32,7 +32,6 @@
|
|||
#define DBSC_REFINTS (0x0)
|
||||
|
||||
/* system registers */
|
||||
#define CPG_BASE (0xE6150000U)
|
||||
#define CPG_FRQCRB (CPG_BASE + 0x0004U)
|
||||
|
||||
#define CPG_PLLECR (CPG_BASE + 0x00D0U)
|
||||
|
@ -56,179 +55,7 @@
|
|||
#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
|
||||
|
||||
/* DBSC registers */
|
||||
#define DBSC_DBSYSCONF1 0xE6790004U
|
||||
#define DBSC_DBPHYCONF0 0xE6790010U
|
||||
#define DBSC_DBKIND 0xE6790020U
|
||||
|
||||
#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
|
||||
#define DBSC_DBMEMCONF_0_0 0xE6790030U
|
||||
#define DBSC_DBMEMCONF_0_1 0xE6790034U
|
||||
#define DBSC_DBMEMCONF_0_2 0xE6790038U
|
||||
#define DBSC_DBMEMCONF_0_3 0xE679003CU
|
||||
#define DBSC_DBMEMCONF_1_2 0xE6790048U
|
||||
#define DBSC_DBMEMCONF_1_3 0xE679004CU
|
||||
#define DBSC_DBMEMCONF_1_0 0xE6790040U
|
||||
#define DBSC_DBMEMCONF_1_1 0xE6790044U
|
||||
#define DBSC_DBMEMCONF_2_0 0xE6790050U
|
||||
#define DBSC_DBMEMCONF_2_1 0xE6790054U
|
||||
#define DBSC_DBMEMCONF_2_2 0xE6790058U
|
||||
#define DBSC_DBMEMCONF_2_3 0xE679005CU
|
||||
#define DBSC_DBMEMCONF_3_0 0xE6790060U
|
||||
#define DBSC_DBMEMCONF_3_1 0xE6790064U
|
||||
#define DBSC_DBMEMCONF_3_2 0xE6790068U
|
||||
#define DBSC_DBMEMCONF_3_3 0xE679006CU
|
||||
|
||||
#define DBSC_DBSYSCNT0 0xE6790100U
|
||||
|
||||
#define DBSC_DBACEN 0xE6790200U
|
||||
#define DBSC_DBRFEN 0xE6790204U
|
||||
#define DBSC_DBCMD 0xE6790208U
|
||||
#define DBSC_DBWAIT 0xE6790210U
|
||||
#define DBSC_DBSYSCTRL0 0xE6790280U
|
||||
|
||||
#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x))
|
||||
#define DBSC_DBTR0 0xE6790300U
|
||||
#define DBSC_DBTR1 0xE6790304U
|
||||
#define DBSC_DBTR3 0xE679030CU
|
||||
#define DBSC_DBTR4 0xE6790310U
|
||||
#define DBSC_DBTR5 0xE6790314U
|
||||
#define DBSC_DBTR6 0xE6790318U
|
||||
#define DBSC_DBTR7 0xE679031CU
|
||||
#define DBSC_DBTR8 0xE6790320U
|
||||
#define DBSC_DBTR9 0xE6790324U
|
||||
#define DBSC_DBTR10 0xE6790328U
|
||||
#define DBSC_DBTR11 0xE679032CU
|
||||
#define DBSC_DBTR12 0xE6790330U
|
||||
#define DBSC_DBTR13 0xE6790334U
|
||||
#define DBSC_DBTR14 0xE6790338U
|
||||
#define DBSC_DBTR15 0xE679033CU
|
||||
#define DBSC_DBTR16 0xE6790340U
|
||||
#define DBSC_DBTR17 0xE6790344U
|
||||
#define DBSC_DBTR18 0xE6790348U
|
||||
#define DBSC_DBTR19 0xE679034CU
|
||||
#define DBSC_DBTR20 0xE6790350U
|
||||
#define DBSC_DBTR21 0xE6790354U
|
||||
#define DBSC_DBTR22 0xE6790358U
|
||||
#define DBSC_DBTR23 0xE679035CU
|
||||
#define DBSC_DBTR24 0xE6790360U
|
||||
#define DBSC_DBTR25 0xE6790364U
|
||||
#define DBSC_DBTR26 0xE6790368U
|
||||
|
||||
#define DBSC_DBBL 0xE6790400U
|
||||
#define DBSC_DBRFCNF1 0xE6790414U
|
||||
#define DBSC_DBRFCNF2 0xE6790418U
|
||||
#define DBSC_DBTSPCNF 0xE6790420U
|
||||
#define DBSC_DBCALCNF 0xE6790424U
|
||||
#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x))
|
||||
#define DBSC_DBRNK2 0xE6790438U
|
||||
#define DBSC_DBRNK3 0xE679043CU
|
||||
#define DBSC_DBRNK4 0xE6790440U
|
||||
#define DBSC_DBRNK5 0xE6790444U
|
||||
#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x))
|
||||
|
||||
#define DBSC_DBADJ0 0xE6790500U
|
||||
#define DBSC_DBDBICNT 0xE6790518U
|
||||
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
|
||||
#define DBSC_DBDFICUPDCNF 0xE679052CU
|
||||
|
||||
#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
|
||||
#define DBSC_DBDFISTAT_0 0xE6790600U
|
||||
#define DBSC_DBDFISTAT_1 0xE6790640U
|
||||
#define DBSC_DBDFISTAT_2 0xE6790680U
|
||||
#define DBSC_DBDFISTAT_3 0xE67906C0U
|
||||
|
||||
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
|
||||
#define DBSC_DBDFICNT_0 0xE6790604U
|
||||
#define DBSC_DBDFICNT_1 0xE6790644U
|
||||
#define DBSC_DBDFICNT_2 0xE6790684U
|
||||
#define DBSC_DBDFICNT_3 0xE67906C4U
|
||||
|
||||
#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT0_0 0xE6790610U
|
||||
#define DBSC_DBPDCNT0_1 0xE6790650U
|
||||
#define DBSC_DBPDCNT0_2 0xE6790690U
|
||||
#define DBSC_DBPDCNT0_3 0xE67906D0U
|
||||
|
||||
#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT1_0 0xE6790614U
|
||||
#define DBSC_DBPDCNT1_1 0xE6790654U
|
||||
#define DBSC_DBPDCNT1_2 0xE6790694U
|
||||
#define DBSC_DBPDCNT1_3 0xE67906D4U
|
||||
|
||||
#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT2_0 0xE6790618U
|
||||
#define DBSC_DBPDCNT2_1 0xE6790658U
|
||||
#define DBSC_DBPDCNT2_2 0xE6790698U
|
||||
#define DBSC_DBPDCNT2_3 0xE67906D8U
|
||||
|
||||
#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT3_0 0xE679061CU
|
||||
#define DBSC_DBPDCNT3_1 0xE679065CU
|
||||
#define DBSC_DBPDCNT3_2 0xE679069CU
|
||||
#define DBSC_DBPDCNT3_3 0xE67906DCU
|
||||
|
||||
#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch))
|
||||
#define DBSC_DBPDLK_0 0xE6790620U
|
||||
#define DBSC_DBPDLK_1 0xE6790660U
|
||||
#define DBSC_DBPDLK_2 0xE67906a0U
|
||||
#define DBSC_DBPDLK_3 0xE67906e0U
|
||||
|
||||
#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGA_0 0xE6790624U
|
||||
#define DBSC_DBPDRGD_0 0xE6790628U
|
||||
#define DBSC_DBPDRGA_1 0xE6790664U
|
||||
#define DBSC_DBPDRGD_1 0xE6790668U
|
||||
#define DBSC_DBPDRGA_2 0xE67906A4U
|
||||
#define DBSC_DBPDRGD_2 0xE67906A8U
|
||||
#define DBSC_DBPDRGA_3 0xE67906E4U
|
||||
#define DBSC_DBPDRGD_3 0xE67906E8U
|
||||
|
||||
#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch))
|
||||
#define DBSC_DBPDSTAT_0 0xE6790630U
|
||||
#define DBSC_DBPDSTAT_1 0xE6790670U
|
||||
#define DBSC_DBPDSTAT_2 0xE67906B0U
|
||||
#define DBSC_DBPDSTAT_3 0xE67906F0U
|
||||
|
||||
#define DBSC_DBBUS0CNF0 0xE6790800U
|
||||
#define DBSC_DBBUS0CNF1 0xE6790804U
|
||||
|
||||
#define DBSC_DBCAM0CNF1 0xE6790904U
|
||||
#define DBSC_DBCAM0CNF2 0xE6790908U
|
||||
#define DBSC_DBCAM0CNF3 0xE679090CU
|
||||
#define DBSC_DBBSWAP 0xE67909F0U
|
||||
#define DBSC_DBBCAMDIS 0xE67909FCU
|
||||
#define DBSC_DBSCHCNT0 0xE6791000U
|
||||
#define DBSC_DBSCHCNT1 0xE6791004U
|
||||
#define DBSC_DBSCHSZ0 0xE6791010U
|
||||
#define DBSC_DBSCHRW0 0xE6791020U
|
||||
#define DBSC_DBSCHRW1 0xE6791024U
|
||||
|
||||
#define DBSC_DBSCHQOS_0(x) (0xE6791030U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_1(x) (0xE6791034U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_2(x) (0xE6791038U +0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_3(x) (0xE679103CU +0x10U * (x))
|
||||
|
||||
#define DBSC_DBSCTR0 0xE6791700U
|
||||
#define DBSC_DBSCTR1 0xE6791708U
|
||||
#define DBSC_DBSCHRW2 0xE679170CU
|
||||
|
||||
#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x))
|
||||
#define DBSC_SCFCTST0 0xE6791700U
|
||||
#define DBSC_SCFCTST1 0xE6791708U
|
||||
#define DBSC_SCFCTST2 0xE679170CU
|
||||
|
||||
#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab))
|
||||
#define DBSC_DBMRRDR_0 0xE6791800U
|
||||
#define DBSC_DBMRRDR_1 0xE6791804U
|
||||
#define DBSC_DBMRRDR_2 0xE6791808U
|
||||
#define DBSC_DBMRRDR_3 0xE679180CU
|
||||
#define DBSC_DBMRRDR_4 0xE6791810U
|
||||
#define DBSC_DBMRRDR_5 0xE6791814U
|
||||
#define DBSC_DBMRRDR_6 0xE6791818U
|
||||
#define DBSC_DBMRRDR_7 0xE679181CU
|
||||
|
||||
#define DBSC_DBMEMSWAPCONF0 0xE6792000U
|
||||
#include "../ddr_regs.h"
|
||||
|
||||
#define DBSC_DBMONCONF4 0xE6793010U
|
||||
|
||||
|
@ -264,33 +91,3 @@
|
|||
/* other module */
|
||||
#define THS1_THCTR 0xE6198020U
|
||||
#define THS1_TEMP 0xE6198028U
|
||||
|
||||
#define DBSC_BASE (0xE6790000U)
|
||||
#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U)
|
||||
#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U)
|
||||
#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U)
|
||||
#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU)
|
||||
#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U)
|
||||
#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U)
|
||||
#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U)
|
||||
#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU)
|
||||
#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U)
|
||||
#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U)
|
||||
#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U)
|
||||
#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU)
|
||||
#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U)
|
||||
#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U)
|
||||
#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U)
|
||||
#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU)
|
||||
#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U)
|
||||
#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U)
|
||||
#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U)
|
||||
#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU)
|
||||
#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U)
|
||||
#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U)
|
||||
#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U)
|
||||
#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU)
|
||||
#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U)
|
||||
#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U)
|
||||
#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U)
|
||||
#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU)
|
||||
|
|
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2019, Renesas Electronics Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef BOOT_INIT_DRAM_REGDEF_H_
|
||||
#define BOOT_INIT_DRAM_REGDEF_H_
|
||||
|
||||
/* DBSC registers */
|
||||
#define DBSC_DBSYSCONF0 0xE6790000U
|
||||
#define DBSC_DBSYSCONF1 0xE6790004U
|
||||
#define DBSC_DBPHYCONF0 0xE6790010U
|
||||
#define DBSC_DBKIND 0xE6790020U
|
||||
#define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
|
||||
#define DBSC_DBMEMCONF_0_0 0xE6790030U
|
||||
#define DBSC_DBMEMCONF_0_1 0xE6790034U
|
||||
#define DBSC_DBMEMCONF_0_2 0xE6790038U
|
||||
#define DBSC_DBMEMCONF_0_3 0xE679003CU
|
||||
#define DBSC_DBMEMCONF_1_2 0xE6790048U
|
||||
#define DBSC_DBMEMCONF_1_3 0xE679004CU
|
||||
#define DBSC_DBMEMCONF_1_0 0xE6790040U
|
||||
#define DBSC_DBMEMCONF_1_1 0xE6790044U
|
||||
#define DBSC_DBMEMCONF_2_0 0xE6790050U
|
||||
#define DBSC_DBMEMCONF_2_1 0xE6790054U
|
||||
#define DBSC_DBMEMCONF_2_2 0xE6790058U
|
||||
#define DBSC_DBMEMCONF_2_3 0xE679005CU
|
||||
#define DBSC_DBMEMCONF_3_0 0xE6790060U
|
||||
#define DBSC_DBMEMCONF_3_1 0xE6790064U
|
||||
#define DBSC_DBMEMCONF_3_2 0xE6790068U
|
||||
#define DBSC_DBMEMCONF_3_3 0xE679006CU
|
||||
#define DBSC_DBSYSCNT0 0xE6790100U
|
||||
#define DBSC_DBSVCR1 0xE6790104U
|
||||
#define DBSC_DBSTATE0 0xE6790108U
|
||||
#define DBSC_DBSTATE1 0xE679010CU
|
||||
#define DBSC_DBINTEN 0xE6790180U
|
||||
#define DBSC_DBINTSTAT0 0xE6790184U
|
||||
#define DBSC_DBACEN 0xE6790200U
|
||||
#define DBSC_DBRFEN 0xE6790204U
|
||||
#define DBSC_DBCMD 0xE6790208U
|
||||
#define DBSC_DBWAIT 0xE6790210U
|
||||
#define DBSC_DBSYSCTRL0 0xE6790280U
|
||||
#define DBSC_DBTR(x) (0xE6790300U + 0x04U * (x))
|
||||
#define DBSC_DBTR0 0xE6790300U
|
||||
#define DBSC_DBTR1 0xE6790304U
|
||||
#define DBSC_DBTR2 0xE6790308U
|
||||
#define DBSC_DBTR3 0xE679030CU
|
||||
#define DBSC_DBTR4 0xE6790310U
|
||||
#define DBSC_DBTR5 0xE6790314U
|
||||
#define DBSC_DBTR6 0xE6790318U
|
||||
#define DBSC_DBTR7 0xE679031CU
|
||||
#define DBSC_DBTR8 0xE6790320U
|
||||
#define DBSC_DBTR9 0xE6790324U
|
||||
#define DBSC_DBTR10 0xE6790328U
|
||||
#define DBSC_DBTR11 0xE679032CU
|
||||
#define DBSC_DBTR12 0xE6790330U
|
||||
#define DBSC_DBTR13 0xE6790334U
|
||||
#define DBSC_DBTR14 0xE6790338U
|
||||
#define DBSC_DBTR15 0xE679033CU
|
||||
#define DBSC_DBTR16 0xE6790340U
|
||||
#define DBSC_DBTR17 0xE6790344U
|
||||
#define DBSC_DBTR18 0xE6790348U
|
||||
#define DBSC_DBTR19 0xE679034CU
|
||||
#define DBSC_DBTR20 0xE6790350U
|
||||
#define DBSC_DBTR21 0xE6790354U
|
||||
#define DBSC_DBTR22 0xE6790358U
|
||||
#define DBSC_DBTR23 0xE679035CU
|
||||
#define DBSC_DBTR24 0xE6790360U
|
||||
#define DBSC_DBTR25 0xE6790364U
|
||||
#define DBSC_DBTR26 0xE6790368U
|
||||
#define DBSC_DBBL 0xE6790400U
|
||||
#define DBSC_DBRFCNF1 0xE6790414U
|
||||
#define DBSC_DBRFCNF2 0xE6790418U
|
||||
#define DBSC_DBTSPCNF 0xE6790420U
|
||||
#define DBSC_DBCALCNF 0xE6790424U
|
||||
#define DBSC_DBRNK(x) (0xE6790430U + 0x04U * (x))
|
||||
#define DBSC_DBRNK2 0xE6790438U
|
||||
#define DBSC_DBRNK3 0xE679043CU
|
||||
#define DBSC_DBRNK4 0xE6790440U
|
||||
#define DBSC_DBRNK5 0xE6790444U
|
||||
#define DBSC_DBPDNCNF 0xE6790450U
|
||||
#define DBSC_DBODT(x) (0xE6790460U + 0x04U * (x))
|
||||
#define DBSC_DBODT0 0xE6790460U
|
||||
#define DBSC_DBODT1 0xE6790464U
|
||||
#define DBSC_DBODT2 0xE6790468U
|
||||
#define DBSC_DBODT3 0xE679046CU
|
||||
#define DBSC_DBODT4 0xE6790470U
|
||||
#define DBSC_DBODT5 0xE6790474U
|
||||
#define DBSC_DBODT6 0xE6790478U
|
||||
#define DBSC_DBODT7 0xE679047CU
|
||||
#define DBSC_DBADJ0 0xE6790500U
|
||||
#define DBSC_DBDBICNT 0xE6790518U
|
||||
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
|
||||
#define DBSC_DBDFICUPDCNF 0xE679052CU
|
||||
#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
|
||||
#define DBSC_DBDFISTAT_0 0xE6790600U
|
||||
#define DBSC_DBDFISTAT_1 0xE6790640U
|
||||
#define DBSC_DBDFISTAT_2 0xE6790680U
|
||||
#define DBSC_DBDFISTAT_3 0xE67906C0U
|
||||
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
|
||||
#define DBSC_DBDFICNT_0 0xE6790604U
|
||||
#define DBSC_DBDFICNT_1 0xE6790644U
|
||||
#define DBSC_DBDFICNT_2 0xE6790684U
|
||||
#define DBSC_DBDFICNT_3 0xE67906C4U
|
||||
#define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT0_0 0xE6790610U
|
||||
#define DBSC_DBPDCNT0_1 0xE6790650U
|
||||
#define DBSC_DBPDCNT0_2 0xE6790690U
|
||||
#define DBSC_DBPDCNT0_3 0xE67906D0U
|
||||
#define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT1_0 0xE6790614U
|
||||
#define DBSC_DBPDCNT1_1 0xE6790654U
|
||||
#define DBSC_DBPDCNT1_2 0xE6790694U
|
||||
#define DBSC_DBPDCNT1_3 0xE67906D4U
|
||||
#define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT2_0 0xE6790618U
|
||||
#define DBSC_DBPDCNT2_1 0xE6790658U
|
||||
#define DBSC_DBPDCNT2_2 0xE6790698U
|
||||
#define DBSC_DBPDCNT2_3 0xE67906D8U
|
||||
#define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch))
|
||||
#define DBSC_DBPDCNT3_0 0xE679061CU
|
||||
#define DBSC_DBPDCNT3_1 0xE679065CU
|
||||
#define DBSC_DBPDCNT3_2 0xE679069CU
|
||||
#define DBSC_DBPDCNT3_3 0xE67906DCU
|
||||
#define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch))
|
||||
#define DBSC_DBPDLK_0 0xE6790620U
|
||||
#define DBSC_DBPDLK_1 0xE6790660U
|
||||
#define DBSC_DBPDLK_2 0xE67906a0U
|
||||
#define DBSC_DBPDLK_3 0xE67906e0U
|
||||
#define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch))
|
||||
#define DBSC_DBPDRGA_0 0xE6790624U
|
||||
#define DBSC_DBPDRGD_0 0xE6790628U
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||||
#define DBSC_DBPDRGA_1 0xE6790664U
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||||
#define DBSC_DBPDRGD_1 0xE6790668U
|
||||
#define DBSC_DBPDRGA_2 0xE67906A4U
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||||
#define DBSC_DBPDRGD_2 0xE67906A8U
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||||
#define DBSC_DBPDRGA_3 0xE67906E4U
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||||
#define DBSC_DBPDRGD_3 0xE67906E8U
|
||||
#define DBSC_DBPDSTAT(ch) (0xE6790630U + 0x40U * (ch))
|
||||
#define DBSC_DBPDSTAT_0 0xE6790630U
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||||
#define DBSC_DBPDSTAT_1 0xE6790670U
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||||
#define DBSC_DBPDSTAT_2 0xE67906B0U
|
||||
#define DBSC_DBPDSTAT_3 0xE67906F0U
|
||||
#define DBSC_DBBUS0CNF0 0xE6790800U
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||||
#define DBSC_DBBUS0CNF1 0xE6790804U
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||||
#define DBSC_DBCAM0CNF1 0xE6790904U
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||||
#define DBSC_DBCAM0CNF2 0xE6790908U
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||||
#define DBSC_DBCAM0CNF3 0xE679090CU
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||||
#define DBSC_DBBSWAP 0xE67909F0U
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||||
#define DBSC_DBBCAMDIS 0xE67909FCU
|
||||
#define DBSC_DBSCHCNT0 0xE6791000U
|
||||
#define DBSC_DBSCHCNT1 0xE6791004U
|
||||
#define DBSC_DBSCHSZ0 0xE6791010U
|
||||
#define DBSC_DBSCHRW0 0xE6791020U
|
||||
#define DBSC_DBSCHRW1 0xE6791024U
|
||||
#define DBSC_DBSCHQOS_0(x) (0xE6791030U + 0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_1(x) (0xE6791034U + 0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_2(x) (0xE6791038U + 0x10U * (x))
|
||||
#define DBSC_DBSCHQOS_3(x) (0xE679103CU + 0x10U * (x))
|
||||
#define DBSC_DBSCHQOS00 0xE6791030U
|
||||
#define DBSC_DBSCHQOS01 0xE6791034U
|
||||
#define DBSC_DBSCHQOS02 0xE6791038U
|
||||
#define DBSC_DBSCHQOS03 0xE679103CU
|
||||
#define DBSC_DBSCHQOS10 0xE6791040U
|
||||
#define DBSC_DBSCHQOS11 0xE6791044U
|
||||
#define DBSC_DBSCHQOS12 0xE6791048U
|
||||
#define DBSC_DBSCHQOS13 0xE679104CU
|
||||
#define DBSC_DBSCHQOS20 0xE6791050U
|
||||
#define DBSC_DBSCHQOS21 0xE6791054U
|
||||
#define DBSC_DBSCHQOS22 0xE6791058U
|
||||
#define DBSC_DBSCHQOS23 0xE679105CU
|
||||
#define DBSC_DBSCHQOS30 0xE6791060U
|
||||
#define DBSC_DBSCHQOS31 0xE6791064U
|
||||
#define DBSC_DBSCHQOS32 0xE6791068U
|
||||
#define DBSC_DBSCHQOS33 0xE679106CU
|
||||
#define DBSC_DBSCHQOS40 0xE6791070U
|
||||
#define DBSC_DBSCHQOS41 0xE6791074U
|
||||
#define DBSC_DBSCHQOS42 0xE6791078U
|
||||
#define DBSC_DBSCHQOS43 0xE679107CU
|
||||
#define DBSC_DBSCHQOS50 0xE6791080U
|
||||
#define DBSC_DBSCHQOS51 0xE6791084U
|
||||
#define DBSC_DBSCHQOS52 0xE6791088U
|
||||
#define DBSC_DBSCHQOS53 0xE679108CU
|
||||
#define DBSC_DBSCHQOS60 0xE6791090U
|
||||
#define DBSC_DBSCHQOS61 0xE6791094U
|
||||
#define DBSC_DBSCHQOS62 0xE6791098U
|
||||
#define DBSC_DBSCHQOS63 0xE679109CU
|
||||
#define DBSC_DBSCHQOS70 0xE67910A0U
|
||||
#define DBSC_DBSCHQOS71 0xE67910A4U
|
||||
#define DBSC_DBSCHQOS72 0xE67910A8U
|
||||
#define DBSC_DBSCHQOS73 0xE67910ACU
|
||||
#define DBSC_DBSCHQOS80 0xE67910B0U
|
||||
#define DBSC_DBSCHQOS81 0xE67910B4U
|
||||
#define DBSC_DBSCHQOS82 0xE67910B8U
|
||||
#define DBSC_DBSCHQOS83 0xE67910BCU
|
||||
#define DBSC_DBSCHQOS90 0xE67910C0U
|
||||
#define DBSC_DBSCHQOS91 0xE67910C4U
|
||||
#define DBSC_DBSCHQOS92 0xE67910C8U
|
||||
#define DBSC_DBSCHQOS93 0xE67910CCU
|
||||
#define DBSC_DBSCHQOS100 0xE67910D0U
|
||||
#define DBSC_DBSCHQOS101 0xE67910D4U
|
||||
#define DBSC_DBSCHQOS102 0xE67910D8U
|
||||
#define DBSC_DBSCHQOS103 0xE67910DCU
|
||||
#define DBSC_DBSCHQOS110 0xE67910E0U
|
||||
#define DBSC_DBSCHQOS111 0xE67910E4U
|
||||
#define DBSC_DBSCHQOS112 0xE67910E8U
|
||||
#define DBSC_DBSCHQOS113 0xE67910ECU
|
||||
#define DBSC_DBSCHQOS120 0xE67910F0U
|
||||
#define DBSC_DBSCHQOS121 0xE67910F4U
|
||||
#define DBSC_DBSCHQOS122 0xE67910F8U
|
||||
#define DBSC_DBSCHQOS123 0xE67910FCU
|
||||
#define DBSC_DBSCHQOS130 0xE6791100U
|
||||
#define DBSC_DBSCHQOS131 0xE6791104U
|
||||
#define DBSC_DBSCHQOS132 0xE6791108U
|
||||
#define DBSC_DBSCHQOS133 0xE679110CU
|
||||
#define DBSC_DBSCHQOS140 0xE6791110U
|
||||
#define DBSC_DBSCHQOS141 0xE6791114U
|
||||
#define DBSC_DBSCHQOS142 0xE6791118U
|
||||
#define DBSC_DBSCHQOS143 0xE679111CU
|
||||
#define DBSC_DBSCHQOS150 0xE6791120U
|
||||
#define DBSC_DBSCHQOS151 0xE6791124U
|
||||
#define DBSC_DBSCHQOS152 0xE6791128U
|
||||
#define DBSC_DBSCHQOS153 0xE679112CU
|
||||
#define DBSC_DBSCTR0 0xE6791700U
|
||||
#define DBSC_DBSCTR1 0xE6791708U
|
||||
#define DBSC_DBSCHRW2 0xE679170CU
|
||||
#define DBSC_SCFCTST01(x) (0xE6791700U + 0x08U * (x))
|
||||
#define DBSC_SCFCTST0 0xE6791700U
|
||||
#define DBSC_SCFCTST1 0xE6791708U
|
||||
#define DBSC_SCFCTST2 0xE679170CU
|
||||
#define DBSC_DBMRRDR(chab) (0xE6791800U + 0x04U * (chab))
|
||||
#define DBSC_DBMRRDR_0 0xE6791800U
|
||||
#define DBSC_DBMRRDR_1 0xE6791804U
|
||||
#define DBSC_DBMRRDR_2 0xE6791808U
|
||||
#define DBSC_DBMRRDR_3 0xE679180CU
|
||||
#define DBSC_DBMRRDR_4 0xE6791810U
|
||||
#define DBSC_DBMRRDR_5 0xE6791814U
|
||||
#define DBSC_DBMRRDR_6 0xE6791818U
|
||||
#define DBSC_DBMRRDR_7 0xE679181CU
|
||||
#define DBSC_DBMEMSWAPCONF0 0xE6792000U
|
||||
|
||||
/* CPG registers */
|
||||
#define CPG_BASE 0xE6150000U
|
||||
#define CPG_FRQCRB (CPG_BASE + 0x0004U)
|
||||
#define CPG_PLLECR (CPG_BASE + 0x00D0U)
|
||||
#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
|
||||
#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
|
||||
#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
|
||||
#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
|
||||
#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
|
||||
#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
|
||||
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
|
||||
#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
|
||||
|
||||
#endif /* BOOT_INIT_DRAM_REGDEF_H_*/
|
|
@ -221,9 +221,11 @@
|
|||
#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
|
||||
#define CPG_PLL2CR (CPG_BASE + 0x002CU)
|
||||
#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
|
||||
#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
|
||||
/* RST Registers */
|
||||
#define RST_BASE (0xE6160000U)
|
||||
#define RST_WDTRSTCR (RST_BASE + 0x0054U)
|
||||
#define RST_MODEMR (RST_BASE + 0x0060U)
|
||||
#define WDTRSTCR_PASSWORD (0xA55A0000U)
|
||||
#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
|
||||
/* MFIS Registers */
|
||||
|
|
Loading…
Reference in New Issue