rcar_get3: drivers: ddr_b: Basic checkpatch fixes
Do basic automated checkpatch fixes on the ddr_b, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie401ec049a05d2c4c8044749994391adea171679
This commit is contained in:
Marek Vasut
parent
f12039be95
commit
a8497fdb72
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@ -45,30 +45,30 @@
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#ifndef RCAR_LSI
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#define RCAR_LSI RCAR_AUTO
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#endif
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#if(RCAR_LSI==RCAR_AUTO)
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#if (RCAR_LSI == RCAR_AUTO)
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static uint32_t Prr_Product;
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static uint32_t Prr_Cut;
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#else
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#if(RCAR_LSI==RCAR_H3)
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#if (RCAR_LSI == RCAR_H3)
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static const uint32_t Prr_Product = PRR_PRODUCT_H3;
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#elif(RCAR_LSI==RCAR_M3)
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#elif(RCAR_LSI == RCAR_M3)
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static const uint32_t Prr_Product = PRR_PRODUCT_M3;
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#elif(RCAR_LSI==RCAR_M3N)
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#elif(RCAR_LSI == RCAR_M3N)
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static const uint32_t Prr_Product = PRR_PRODUCT_M3N;
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#elif(RCAR_LSI==RCAR_H3N)
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#elif(RCAR_LSI == RCAR_H3N)
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static const uint32_t Prr_Product = PRR_PRODUCT_H3;
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#endif /* RCAR_LSI */
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#ifndef RCAR_LSI_CUT
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static uint32_t Prr_Cut;
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#else /* RCAR_LSI_CUT */
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#if(RCAR_LSI_CUT==RCAR_CUT_10)
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#if (RCAR_LSI_CUT == RCAR_CUT_10)
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static const uint32_t Prr_Cut = PRR_PRODUCT_10;
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#elif(RCAR_LSI_CUT==RCAR_CUT_11)
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#elif(RCAR_LSI_CUT == RCAR_CUT_11)
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static const uint32_t Prr_Cut = PRR_PRODUCT_11;
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#elif(RCAR_LSI_CUT==RCAR_CUT_20)
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#elif(RCAR_LSI_CUT == RCAR_CUT_20)
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static const uint32_t Prr_Cut = PRR_PRODUCT_20;
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#elif(RCAR_LSI_CUT==RCAR_CUT_30)
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#elif(RCAR_LSI_CUT == RCAR_CUT_30)
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static const uint32_t Prr_Cut = PRR_PRODUCT_30;
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#endif /* RCAR_LSI_CUT */
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#endif /* RCAR_LSI_CUT */
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@ -130,7 +130,7 @@ uint32_t ddrBackup;
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#define OPERATING_FREQ (400U) /* Mhz */
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#define BASE_SUB_SLOT_NUM (0x6U)
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#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
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#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
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#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) /* unit:ns */
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uint32_t get_refperiod(void)
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{
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@ -249,21 +249,21 @@ static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
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static void ddr_setval_ach(uint32_t regdef, uint32_t val);
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static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
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static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
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static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p);
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static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p);
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static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size);
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static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val);
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static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef);
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static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
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static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
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static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
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static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
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static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
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static uint32_t ddrphy_regif_chk(void);
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static inline void ddrphy_regif_idle();
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static inline void ddrphy_regif_idle(void);
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static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
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uint16_t cyc);
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static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
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uint16_t * js2);
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uint16_t *js2);
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static int16_t _f_scale_adj(int16_t ps);
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static void ddrtbl_load(void);
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static void ddr_config_sub(void);
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static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz);
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static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
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static void ddr_config_sub_h3v1x(void);
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static void ddr_config(void);
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static void dbsc_regset(void);
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@ -297,6 +297,7 @@ struct DdrtData {
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uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */
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uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */
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};
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struct DdrtData tcal;
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static void pvtcode_update(void);
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@ -341,10 +342,10 @@ static inline uint32_t vch_nxt(uint32_t pos)
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}
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#define foreach_vch(ch) \
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for(ch=vch_nxt(0);ch<DRAM_CH_CNT;ch=vch_nxt(ch+1))
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for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1))
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#define foreach_ech(ch) \
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for(ch=0;ch<DRAM_CH_CNT;ch++)
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for (ch = 0; ch < DRAM_CH_CNT; ch++)
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/*******************************************************************************
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* Printing functions
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@ -532,8 +533,8 @@ static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
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uint32_t loop;
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val = 0;
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if ((PRR_PRODUCT_M3N != Prr_Product)
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&& (PRR_PRODUCT_V3H != Prr_Product)) {
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if ((Prr_Product != PRR_PRODUCT_M3N)
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&& (Prr_Product != PRR_PRODUCT_V3H)) {
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mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
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dsb_sev();
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@ -579,8 +580,8 @@ static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
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uint32_t val;
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uint32_t loop;
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if ((PRR_PRODUCT_M3N != Prr_Product)
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&& (PRR_PRODUCT_V3H != Prr_Product)) {
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if ((Prr_Product != PRR_PRODUCT_M3N)
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&& (Prr_Product != PRR_PRODUCT_V3H)) {
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mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
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dsb_sev();
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for (loop = 0; loop < loop_max; loop++) {
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@ -628,8 +629,8 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
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uint32_t val;
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uint32_t loop;
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if ((PRR_PRODUCT_M3N != Prr_Product)
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&& (PRR_PRODUCT_V3H != Prr_Product)) {
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if ((Prr_Product != PRR_PRODUCT_M3N)
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&& (Prr_Product != PRR_PRODUCT_V3H)) {
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foreach_vch(ch) {
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mmio_write_32(DBSC_DBPDRGA(ch), regadd);
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dsb_sev();
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@ -653,7 +654,7 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
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}
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}
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static inline void ddrphy_regif_idle()
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static inline void ddrphy_regif_idle(void)
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{
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uint32_t val;
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@ -759,7 +760,7 @@ static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
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return ddr_getval_s(ch, 0, regdef);
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}
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static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p)
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static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
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{
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uint32_t ch;
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@ -768,7 +769,7 @@ static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p)
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return p[0];
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}
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static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p)
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static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
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{
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uint32_t ch, slice;
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uint32_t *pp;
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@ -783,7 +784,7 @@ static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p)
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/*******************************************************************************
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* handling functions for setteing ddrphy value table
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******************************************************************************/
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static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size)
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static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
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{
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uint32_t i;
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@ -792,7 +793,7 @@ static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size)
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}
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}
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static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val)
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static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
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{
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uint32_t adr;
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uint32_t lsb;
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@ -822,7 +823,7 @@ static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val)
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tbl[adr & adrmsk] = tmp;
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}
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static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef)
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static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
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{
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uint32_t adr;
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uint32_t lsb;
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@ -870,10 +871,10 @@ static uint32_t ddrphy_regif_chk(void)
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PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */
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}
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ddr_getval_ach(_reg_PI_VERSION, (uint32_t *) tmp_ach);
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ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
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err = 0;
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foreach_vch(ch) {
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if (PI_VERSION_CODE != tmp_ach[ch])
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if (tmp_ach[ch] != PI_VERSION_CODE)
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err = 1;
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}
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return err;
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@ -892,15 +893,16 @@ struct _jedec_spec1 {
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uint8_t MR1;
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uint8_t MR2;
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};
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#define JS1_USABLEC_SPEC_LO 2
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#define JS1_USABLEC_SPEC_HI 5
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#define JS1_FREQ_TBL_NUM 8
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#define JS1_MR1(f) (0x04 | ((f)<<4))
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#define JS1_MR2(f) (0x00 | ((f)<<3) | (f))
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#define JS1_MR1(f) (0x04 | ((f) << 4))
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#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
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const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
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{ 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0)|0x40 }, /* 533.333Mbps */
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{ 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1)|0x40 }, /* 1066.666Mbps */
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{ 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2)|0x40 }, /* 1600.000Mbps */
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{ 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40 }, /* 533.333Mbps */
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{ 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40 }, /* 1066.666Mbps */
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{ 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40 }, /* 1600.000Mbps */
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{ 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, /* 2133.333Mbps */
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{ 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, /* 2666.666Mbps */
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{ 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, /* 3200.000Mbps */
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@ -938,9 +940,9 @@ struct _jedec_spec2 {
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#define JS2_TBLCNT 22
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#define JS2_tRCpb (JS2_TBLCNT)
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#define JS2_tRCab (JS2_TBLCNT+1)
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#define JS2_tRFCab (JS2_TBLCNT+2)
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#define JS2_CNT (JS2_TBLCNT+3)
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#define JS2_tRCab (JS2_TBLCNT + 1)
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#define JS2_tRFCab (JS2_TBLCNT + 2)
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#define JS2_CNT (JS2_TBLCNT + 3)
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#ifndef JS2_DERATE
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#define JS2_DERATE 0
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@ -1011,18 +1013,18 @@ static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
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uint32_t tmp;
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uint32_t div;
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tmp = (((uint32_t) (ps) + 9) / 10) * ddr_mbps;
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tmp = (((uint32_t)(ps) + 9) / 10) * ddr_mbps;
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div = tmp / (200000 * ddr_mbpsdiv);
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if (tmp != (div * 200000 * ddr_mbpsdiv))
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div = div + 1;
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if (div > cyc)
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return (uint16_t) div;
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return (uint16_t)div;
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return cyc;
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}
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static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
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uint16_t * js2)
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uint16_t *js2)
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{
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int i;
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@ -1046,11 +1048,11 @@ static int16_t _f_scale_adj(int16_t ps)
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= ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
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*/
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tmp =
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(int32_t) 4 *(int32_t) ps *(int32_t) ddr_mbps /
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(int32_t) ddr_mbpsdiv;
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tmp = (int32_t) tmp / (int32_t) 15625;
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(int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
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(int32_t)ddr_mbpsdiv;
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tmp = (int32_t)tmp / (int32_t)15625;
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return (int16_t) tmp;
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return (int16_t)tmp;
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}
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const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = {
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@ -1220,7 +1222,7 @@ static void regif_pll_wa(void)
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foreach_ech(ch)
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if (((Boardcnf->phyvalid) & (1U << ch)))
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while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) ;
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while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f);
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dsb_sev();
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}
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@ -1245,7 +1247,7 @@ static void ddrtbl_load(void)
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if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
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break;
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}
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if (JS1_USABLEC_SPEC_HI < i)
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if (i > JS1_USABLEC_SPEC_HI)
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js1_ind = JS1_USABLEC_SPEC_HI;
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else
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js1_ind = i;
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@ -1624,6 +1626,7 @@ static void ddr_config_sub(void)
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uint32_t tmp;
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uint8_t high_byte[SLICE_CNT];
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const uint32_t _par_CALVL_DEVICE_MAP = 1;
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foreach_vch(ch) {
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/***********************************************************************
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BOARD SETTINGS (DQ,DM,VREF_DRIVING)
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@ -1747,11 +1750,12 @@ static void ddr_config_sub(void)
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}
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}
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static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
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static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
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{
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uint32_t slice;
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uint32_t tmp;
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uint32_t tgt;
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if (ddr_csn / 2) {
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tgt = 3;
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} else {
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@ -2275,11 +2279,11 @@ static void dbsc_regset(void)
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if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
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mmio_write_32(DBSC_DBSCHRW1, tmp[0]
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+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
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* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3);
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* 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3);
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} else {
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mmio_write_32(DBSC_DBSCHRW1, tmp[0]
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+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
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* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps);
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* 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps);
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}
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/***********************************************************************
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@ -2651,6 +2655,7 @@ static uint32_t set_term_code(void)
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uint32_t pvtr;
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uint32_t pvtp;
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uint32_t pvtn;
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term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
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_reg_PHY_PAD_DATA_TERM);
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override = 0;
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@ -2801,6 +2806,7 @@ static inline uint32_t wait_freqchgreq(uint32_t assert)
|
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uint32_t dataL;
|
||||
uint32_t count;
|
||||
uint32_t ch;
|
||||
|
||||
count = 100000;
|
||||
|
||||
/* H3 Ver.1.x cannot see frqchg_req */
|
||||
|
|
@ -2833,6 +2839,7 @@ static inline void set_freqchgack(uint32_t assert)
|
|||
{
|
||||
uint32_t ch;
|
||||
uint32_t dataL;
|
||||
|
||||
if (assert)
|
||||
dataL = 0x0CF20000;
|
||||
else
|
||||
|
|
@ -2845,6 +2852,7 @@ static inline void set_freqchgack(uint32_t assert)
|
|||
static inline void set_dfifrequency(uint32_t freq)
|
||||
{
|
||||
uint32_t ch;
|
||||
|
||||
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
|
||||
foreach_vch(ch)
|
||||
mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
|
||||
|
|
@ -3404,7 +3412,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
|
|||
_reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
|
||||
wdqdm_le[ch][cs][slice][i] = dataL;
|
||||
win =
|
||||
(int32_t) wdqdm_te[ch][cs][slice][i] -
|
||||
(int32_t)wdqdm_te[ch][cs][slice][i] -
|
||||
wdqdm_le[ch][cs][slice][i];
|
||||
if (min_win > win)
|
||||
min_win = win;
|
||||
|
|
@ -3825,7 +3833,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
|
|||
dataL;
|
||||
|
||||
win =
|
||||
(int32_t) rdqdm_te[ch][cs][slice +
|
||||
(int32_t)rdqdm_te[ch][cs][slice +
|
||||
SLICE_CNT *
|
||||
k][i] -
|
||||
rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
|
||||
|
|
@ -4043,7 +4051,7 @@ static uint32_t rx_offset_cal(void)
|
|||
ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
|
||||
}
|
||||
dsb_sev();
|
||||
ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as);
|
||||
ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
|
||||
|
||||
foreach_vch(ch) {
|
||||
for (slice = 0; slice < SLICE_CNT; slice++) {
|
||||
|
|
@ -4140,6 +4148,7 @@ static void adjust_rddqs_latency(void)
|
|||
uint32_t maxlatx2;
|
||||
uint32_t tmp;
|
||||
uint32_t rdlat_adjx2[SLICE_CNT];
|
||||
|
||||
foreach_vch(ch) {
|
||||
maxlatx2 = 0;
|
||||
for (slice = 0; slice < SLICE_CNT; slice++) {
|
||||
|
|
@ -4236,7 +4245,7 @@ int32_t rcar_dram_init(void)
|
|||
Judge product and cut
|
||||
***********************************************************************/
|
||||
#ifdef RCAR_DDR_FIXED_LSI_TYPE
|
||||
#if(RCAR_LSI==RCAR_AUTO)
|
||||
#if (RCAR_LSI == RCAR_AUTO)
|
||||
Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
|
||||
Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
|
||||
#else /* RCAR_LSI */
|
||||
|
|
@ -4340,8 +4349,7 @@ int32_t rcar_dram_init(void)
|
|||
|
||||
ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
|
||||
|
||||
ddr_mul =
|
||||
CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
|
||||
ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
|
||||
brd_clkdiv * (brd_clkdiva + 1));
|
||||
|
||||
/***********************************************************************
|
||||
|
|
@ -4487,6 +4495,7 @@ void pvtcode_update(void)
|
|||
void pvtcode_update2(void)
|
||||
{
|
||||
uint32_t ch;
|
||||
|
||||
foreach_vch(ch) {
|
||||
reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
|
||||
tcal.init_cal[ch] | 0x00020000);
|
||||
|
|
@ -4522,27 +4531,27 @@ void ddr_padcal_tcompensate_getinit(uint32_t override)
|
|||
dataL = mmio_read_32(THS1_TEMP);
|
||||
if (dataL < 2800) {
|
||||
tcal.init_temp =
|
||||
(143 * (int32_t) dataL - 359000) / 1000;
|
||||
(143 * (int32_t)dataL - 359000) / 1000;
|
||||
} else {
|
||||
tcal.init_temp =
|
||||
(121 * (int32_t) dataL - 296300) / 1000;
|
||||
(121 * (int32_t)dataL - 296300) / 1000;
|
||||
}
|
||||
|
||||
foreach_vch(ch) {
|
||||
pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F;
|
||||
pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F;
|
||||
if ((int32_t) pvtp >
|
||||
if ((int32_t)pvtp >
|
||||
((tcal.init_temp * 29 - 3625) / 1000))
|
||||
pvtp =
|
||||
(int32_t) pvtp +
|
||||
(int32_t)pvtp +
|
||||
((3625 - tcal.init_temp * 29) / 1000);
|
||||
else
|
||||
pvtp = 0;
|
||||
|
||||
if ((int32_t) pvtn >
|
||||
if ((int32_t)pvtn >
|
||||
((tcal.init_temp * 54 - 6750) / 1000))
|
||||
pvtn =
|
||||
(int32_t) pvtn +
|
||||
(int32_t)pvtn +
|
||||
((6750 - tcal.init_temp * 54) / 1000);
|
||||
else
|
||||
pvtn = 0;
|
||||
|
|
|
|||
|
|
@ -1529,7 +1529,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
|
|||
}
|
||||
};
|
||||
|
||||
void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
|
||||
void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
|
||||
{
|
||||
uint32_t md;
|
||||
|
||||
|
|
@ -1560,7 +1560,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
|
|||
(void)brd;
|
||||
}
|
||||
|
||||
void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
|
||||
void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
|
||||
{
|
||||
uint32_t md;
|
||||
|
||||
|
|
@ -1630,7 +1630,7 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v)
|
|||
mmio_write_32(PFC_PMMR, ~v);
|
||||
v = ~mmio_read_32(PFC_PMMR);
|
||||
mmio_write_32(a, v);
|
||||
while (v != mmio_read_32(a)) ;
|
||||
while (v != mmio_read_32(a));
|
||||
dsb_sev();
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1699,7 +1699,7 @@ static uint32_t opencheck_SSI_WS6(void)
|
|||
static uint32_t _board_judge(void)
|
||||
{
|
||||
uint32_t brd;
|
||||
#if (RCAR_GEN3_ULCB==1)
|
||||
#if (RCAR_GEN3_ULCB == 1)
|
||||
/* Starter Kit */
|
||||
if (Prr_Product == PRR_PRODUCT_H3) {
|
||||
if (Prr_Cut <= PRR_PRODUCT_11) {
|
||||
|
|
@ -1725,7 +1725,7 @@ static uint32_t _board_judge(void)
|
|||
|
||||
usb2_ovc_open = opencheck_SSI_WS6();
|
||||
|
||||
/* RENESAS Eva-borad */
|
||||
/* RENESAS Eva-board */
|
||||
brd = 99;
|
||||
if (Prr_Product == PRR_PRODUCT_V3H) {
|
||||
/* RENESAS Condor board */
|
||||
|
|
@ -1738,7 +1738,7 @@ static uint32_t _board_judge(void)
|
|||
/* RENESAS Kriek board with M3-W */
|
||||
brd = 1;
|
||||
} else if ((Prr_Product == PRR_PRODUCT_H3)
|
||||
&& (Prr_Cut<=PRR_PRODUCT_11)) {
|
||||
&& (Prr_Cut <= PRR_PRODUCT_11)) {
|
||||
/* RENESAS Kriek board with PM3 */
|
||||
brd = 13;
|
||||
} else if ((Prr_Product == PRR_PRODUCT_H3)
|
||||
|
|
|
|||
|
|
@ -1178,9 +1178,9 @@
|
|||
#define _reg_PI_TSDO_F1 0x00000493U
|
||||
#define _reg_PI_TSDO_F2 0x00000494U
|
||||
|
||||
#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff)
|
||||
#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
|
||||
#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
|
||||
#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff)
|
||||
#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff)
|
||||
#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff)
|
||||
|
||||
static const uint32_t DDR_REGDEF_TBL[4][1173] = {
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue