Merge changes I9c7cc586,I48ee254a,I9f65c6af,I5872d95b,I2dbbdcb4, ... into integration
* changes: feat(docs/nxp/layerscape): add ls1028a soc and board support feat(plat/nxp/ls1028ardb): add ls1028ardb board support feat(plat/nxp/ls1028a): add ls1028a soc support feat(plat/nxp/common): define default SD buffer feat(driver/nxp/xspi): add MT35XU02G flash info feat(plat/nxp/common): add SecMon register definition for ch_3_2 feat(driver/nxp/dcfg): define RSTCR_RESET_REQ feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS feat(plat/nxp/common): define default PSCI features if not defined feat(plat/nxp/common): define common macro for ARM registers feat(plat/nxp/common): add CCI and EPU address definition
This commit is contained in:
Joanna Farley
TrustedFirmware Code Review
commit
ab5964aadc
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@ -5,22 +5,62 @@ NXP SoCs - Overview
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The QorIQ family of ARM based SoCs that are supported on TF-A are:
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1. LX2160ARDB:
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Platform Name:
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1. LX2160A
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a. lx2160ardb (Board details can be fetched from the link: `lx2160ardb`_)
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- SoC Overview:
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The LX2160A multicore processor, the highest-performance member of the
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Layerscape family, combines FinFET process technology's low power and
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sixteen Arm® Cortex®-A72 cores with datapath acceleration optimized for
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L2/3 packet processing, together with security offload, robust traffic
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management and quality of service.
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Details about LX2160A can be found at `lx2160a`_.
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- LX2160ARDB Board:
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The LX2160A reference design board provides a comprehensive platform
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that enables design and evaluation of the LX2160A or LX2162A processors. It
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comes preloaded with a board support package (BSP) based on a standard Linux
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kernel.
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Board details can be fetched from the link: `lx2160ardb`_.
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2. LS1028A
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- SoC Overview:
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The Layerscape LS1028A applications processor for industrial and
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automotive includes a time-sensitive networking (TSN) -enabled Ethernet
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switch and Ethernet controllers to support converged IT and OT networks.
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Two powerful 64-bit Arm®v8 cores support real-time processing for
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industrial control and virtual machines for edge computing in the IoT.
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The integrated GPU and LCD controller enable Human-Machine Interface
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(HMI) systems with next-generation interfaces.
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Details about LS1028A can be found at `ls1028a`_.
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- LS1028ARDB Boards:
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The LS1028A reference design board (RDB) is a computing, evaluation,
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and development platform that supports industrial IoT applications, human
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machine interface solutions, and industrial networking.
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Details about LS1028A RDB board can be found at `ls1028ardb`_.
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Table of supported boot-modes by each platform & platform that needs FIP-DDR:
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-----------------------------------------------------------------------------
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+---+-----------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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| | BOOT_MODE-->| sd | qspi | nor | nand | emmc | flexspi_nor | flexspi_nand | fip_ddr needed |
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| | | | | | | | | | |
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| | PLAT | | | | | | | | |
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+===+=================+=======+========+=======+=======+=======+=============+==============+=================+
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| 1.| lx2160ardb | yes | | | | yes | yes | | yes |
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+---+-----------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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+---------------------+---------------------------------------------------------------------+-----------------+
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| | BOOT_MODE | |
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| PLAT +-------+--------+-------+-------+-------+-------------+--------------+ fip_ddr_needed |
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| | sd | qspi | nor | nand | emmc | flexspi_nor | flexspi_nand | |
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+=====================+=======+========+=======+=======+=======+=============+==============+=================+
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| lx2160ardb | yes | | | | yes | yes | | yes |
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+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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| ls1028ardb | yes | | | | yes | yes | | no |
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+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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Boot Sequence
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-------------
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@ -54,6 +94,32 @@ Boot Sequence with FIP-DDR
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+ EL3 BootROM --> BL2 -----> BL31 ---------------/
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+
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DDR Memory Layout
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--------------------------
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NXP Platforms divide DRAM into banks:
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- DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h if it is less than 2GB.
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- DRAM1 ~ DRAMn Bank: Greater than 2GB belongs to DRAM1 and following banks, and size of DRAMn Bank varies for one platform to others.
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The following diagram is default DRAM0 memory layout in which secure memory is at top of DRAM0.
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::
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high +---------------------------------------------+
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| |
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| Secure EL1 Payload Shared Memory (2 MB) |
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| |
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+---------------------------------------------+
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| |
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| Secure Memory (64 MB) |
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| |
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+---------------------------------------------+
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| |
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| Non Secure Memory |
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| |
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low +---------------------------------------------+
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How to build
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=============
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@ -228,5 +294,8 @@ For TBBR, the binary name changes:
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Refer `nxp-ls-tbbr.rst`_ for detailed user steps.
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.. _lx2160a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A
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.. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A
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.. _ls1028a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1028a-applications-processor:LS1028A
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.. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB
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.. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst
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@ -74,4 +74,7 @@
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#define DCFG_BOOTLOCPTRH_OFFSET 0x404
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#define DCFG_COREDISABLEDSR_OFFSET 0x990
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/* Reset module bit field */
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#define RSTCR_RESET_REQ 0x2
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#endif /* DCFG_LSCH3_H */
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright 2020 NXP
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* Copyright 2020-2021 NXP
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*/
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/**
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@ -53,6 +53,16 @@
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#define F_SECTOR_ERASE_SZ F_SECTOR_4K
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#endif
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#elif defined(CONFIG_MT35XU02G)
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#define F_SECTOR_128K 0x20000U
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#define F_PAGE_256 0x100U
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#define F_SECTOR_4K 0x1000U
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#define F_FLASH_SIZE_BYTES 0x10000000U
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#define F_SECTOR_ERASE_SZ F_SECTOR_128K
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#ifdef CONFIG_FSPI_4K_ERASE
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#define F_SECTOR_ERASE_SZ F_SECTOR_4K
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#endif
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#ifdef NXP_WARM_BOOT
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#define FLASH_WR_COMP_WAIT_BY_NOP_COUNT 0x20000
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#endif
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@ -23,6 +23,9 @@
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/* MMU 500 soc.c*/
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#define NXP_SMMU_ADDR 0x05000000
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/* CCI400 base address */
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#define NXP_CCI_ADDR 0x04090000
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#define NXP_SNVS_ADDR 0x01E90000
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#define NXP_DCFG_ADDR 0x01E00000
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@ -81,4 +84,5 @@
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#define NXP_CCN_HNI_ADDR 0x04080000
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#define NXP_CCN_HN_F_0_ADDR 0x04200000
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#define NXP_EPU_ADDR 0x700060000
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#endif /* SOC_DEFAULT_BASE_ADDR_H */
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@ -39,6 +39,10 @@
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#endif /* NXP_RESET_ADDR */
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/* secmon register offsets and bitfields */
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#define SECMON_HPCOMR_OFFSET 0x4
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#define SECMON_HPCOMR_NPSWAEN 0x80000000
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/* Secure-Register-File register offsets and bit masks */
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#ifdef NXP_RST_ADDR
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/* Register Offset */
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@ -40,8 +40,12 @@
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#define NXP_NS_DRAM_ADDR NXP_DRAM0_ADDR
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#endif
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/* 64M is reserved for Secure memory
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*/
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/* 1 MB is reserved for dma of sd */
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#ifndef NXP_SD_BLOCK_BUF_SIZE
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#define NXP_SD_BLOCK_BUF_SIZE (1 * 1024 * 1024)
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#endif
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/* 64MB is reserved for Secure memory */
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#ifndef NXP_SECURE_DRAM_SIZE
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#define NXP_SECURE_DRAM_SIZE (64 * 1024 * 1024)
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#endif
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@ -57,18 +61,22 @@
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
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#endif
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#ifndef NXP_SD_BLOCK_BUF_ADDR
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#define NXP_SD_BLOCK_BUF_ADDR (NXP_NS_DRAM_ADDR)
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#endif
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#ifndef NXP_SECURE_DRAM_ADDR
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#ifdef TEST_BL31
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#define NXP_SECURE_DRAM_ADDR 0
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#else
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#define NXP_SECURE_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE - \
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
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(NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
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#endif
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#endif
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#ifndef NXP_SP_SHRD_DRAM_ADDR
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#define NXP_SP_SHRD_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE \
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- NXP_SP_SHRD_DRAM_SIZE)
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#define NXP_SP_SHRD_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE - \
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NXP_SP_SHRD_DRAM_SIZE)
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#endif
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#ifndef BL31_BASE
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@ -1,6 +1,6 @@
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/*
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* Copyright 2018-2020 NXP
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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@ -234,7 +234,7 @@ func _psci_cpu_prep_off
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msr DAIFSet, #0xF
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/* read cpuectlr and save current value */
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mrs x4, CORTEX_A72_ECTLR_EL1
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mrs x4, CPUECTLR_EL1
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mov x1, #CPUECTLR_DATA
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mov x2, x4
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mov x0, x10
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@ -242,7 +242,7 @@ func _psci_cpu_prep_off
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/* remove the core from coherency */
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bic x4, x4, #CPUECTLR_SMPEN_MASK
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msr CORTEX_A72_ECTLR_EL1, x4
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msr CPUECTLR_EL1, x4
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/* save scr_el3 */
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mov x0, x10
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@ -339,7 +339,7 @@ func _psci_wakeup
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mov x1, #CPUECTLR_DATA
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bl _getCoreData
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orr x0, x0, #CPUECTLR_SMPEN_MASK
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msr CORTEX_A72_ECTLR_EL1, x0
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msr CPUECTLR_EL1, x0
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/* x4 = core mask */
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@ -563,7 +563,7 @@ func _psci_core_prep_pwrdn
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/* save cpuectlr */
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mov x0, x6
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mov x1, #CPUECTLR_DATA
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mrs x2, CORTEX_A72_ECTLR_EL1
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mrs x2, CPUECTLR_EL1
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bl _setCoreData
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/* x6 = core mask */
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@ -640,7 +640,7 @@ func _psci_core_exit_pwrdn
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bl _getCoreData
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/* make sure smp is set */
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orr x0, x0, #CPUECTLR_SMPEN_MASK
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msr CORTEX_A72_ECTLR_EL1, x0
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msr CPUECTLR_EL1, x0
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/* x5 = core mask */
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@ -780,13 +780,13 @@ func _psci_clstr_prep_pwrdn
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/* save cpuectlr */
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mov x0, x6
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mov x1, #CPUECTLR_DATA
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mrs x2, CORTEX_A72_ECTLR_EL1
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mrs x2, CPUECTLR_EL1
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mov x4, x2
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bl _setCoreData
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/* remove core from coherency */
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bic x4, x4, #CPUECTLR_SMPEN_MASK
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msr CORTEX_A72_ECTLR_EL1, x4
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msr CPUECTLR_EL1, x4
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/* x6 = core mask */
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@ -844,7 +844,7 @@ func _psci_clstr_exit_pwrdn
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bl _getCoreData
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/* make sure smp is set */
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orr x0, x0, #CPUECTLR_SMPEN_MASK
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msr CORTEX_A72_ECTLR_EL1, x0
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msr CPUECTLR_EL1, x0
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/* x4 = core mask */
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@ -985,13 +985,13 @@ func _psci_sys_prep_pwrdn
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/* save cpuectlr */
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mov x0, x6
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mov x1, #CPUECTLR_DATA
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mrs x2, CORTEX_A72_ECTLR_EL1
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mrs x2, CPUECTLR_EL1
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mov x4, x2
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bl _setCoreData
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/* remove core from coherency */
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bic x4, x4, #CPUECTLR_SMPEN_MASK
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msr CORTEX_A72_ECTLR_EL1, x4
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msr CPUECTLR_EL1, x4
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/* x6 = core mask */
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|
|
@ -1071,7 +1071,7 @@ func _psci_sys_exit_pwrdn
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|
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/* make sure smp is set */
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orr x0, x0, #CPUECTLR_SMPEN_MASK
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msr CORTEX_A72_ECTLR_EL1, x0
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msr CPUECTLR_EL1, x0
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/* x4 = core mask */
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|
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|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
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* Copyright 2018-2020 NXP
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
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|
|
@ -7,6 +7,8 @@
|
|||
|
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#ifndef PLAT_PSCI_H
|
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#define PLAT_PSCI_H
|
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#include <cortex_a53.h>
|
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#include <cortex_a72.h>
|
||||
|
||||
/* core abort current op */
|
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#define CORE_ABORT_OP 0x1
|
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|
|
@ -55,6 +57,7 @@
|
|||
#define CPUECTLR_RET_SET 0x2
|
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#define CPUECTLR_TIMER_MASK 0x7
|
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#define CPUECTLR_TIMER_8TICKS 0x2
|
||||
#define CPUECTLR_TIMER_2TICKS 0x1
|
||||
#define SCR_IRQ_MASK 0x2
|
||||
#define SCR_FIQ_MASK 0x4
|
||||
|
||||
|
|
@ -62,18 +65,53 @@
|
|||
* value == 0x0, the soc code does not support this feature
|
||||
* value != 0x0, the soc code supports this feature
|
||||
*/
|
||||
#ifndef SOC_CORE_RELEASE
|
||||
#define SOC_CORE_RELEASE 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_CORE_RESTART
|
||||
#define SOC_CORE_RESTART 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_CORE_OFF
|
||||
#define SOC_CORE_OFF 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_CORE_STANDBY
|
||||
#define SOC_CORE_STANDBY 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_CORE_PWR_DWN
|
||||
#define SOC_CORE_PWR_DWN 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_CLUSTER_STANDBY
|
||||
#define SOC_CLUSTER_STANDBY 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_CLUSTER_PWR_DWN
|
||||
#define SOC_CLUSTER_PWR_DWN 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_SYSTEM_STANDBY
|
||||
#define SOC_SYSTEM_STANDBY 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_SYSTEM_PWR_DWN
|
||||
#define SOC_SYSTEM_PWR_DWN 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_SYSTEM_OFF
|
||||
#define SOC_SYSTEM_OFF 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_SYSTEM_RESET
|
||||
#define SOC_SYSTEM_RESET 0x1
|
||||
#endif
|
||||
|
||||
#ifndef SOC_SYSTEM_RESET2
|
||||
#define SOC_SYSTEM_RESET2 0x1
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright 2018-2020 NXP
|
||||
# Copyright 2018-2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -11,9 +11,11 @@
|
|||
|
||||
CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
|
||||
|
||||
ifeq (,$(filter $(CORE_TYPE),a53 a55 a57 a72 a75))
|
||||
ifeq (,$(filter $(CORE_TYPE),a53 a72))
|
||||
$(error "CORE_TYPE not specified or incorrect")
|
||||
else
|
||||
UPPER_CORE_TYPE=$(shell echo $(CORE_TYPE) | tr a-z A-Z)
|
||||
$(eval $(call add_define_val,CPUECTLR_EL1,CORTEX_$(UPPER_CORE_TYPE)_ECTLR_EL1))
|
||||
CPU_LIBS += lib/cpus/${ARCH}/cortex_$(CORE_TYPE).S
|
||||
endif
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
.globl plat_secondary_cold_boot_setup
|
||||
.globl plat_is_my_cpu_primary
|
||||
.globl plat_reset_handler
|
||||
.globl platform_mem_init
|
||||
|
||||
func platform_mem1_init
|
||||
ret
|
||||
endfunc platform_mem1_init
|
||||
|
||||
func platform_mem_init
|
||||
ret
|
||||
endfunc platform_mem_init
|
||||
|
||||
func apply_platform_errata
|
||||
ret
|
||||
endfunc apply_platform_errata
|
||||
|
||||
func plat_reset_handler
|
||||
mov x29, x30
|
||||
bl apply_platform_errata
|
||||
|
||||
#if defined(IMAGE_BL31)
|
||||
ldr x0, =POLICY_SMMU_PAGESZ_64K
|
||||
cbz x0, 1f
|
||||
/* Set the SMMU page size in the sACR register */
|
||||
bl _set_smmu_pagesz_64
|
||||
#endif
|
||||
1:
|
||||
mov x30, x29
|
||||
ret
|
||||
endfunc plat_reset_handler
|
||||
|
||||
/*
|
||||
* void plat_secondary_cold_boot_setup (void);
|
||||
*
|
||||
* This function performs any platform specific actions
|
||||
* needed for a secondary cpu after a cold reset e.g
|
||||
* mark the cpu's presence, mechanism to place it in a
|
||||
* holding pen etc.
|
||||
*/
|
||||
func plat_secondary_cold_boot_setup
|
||||
/* ls1028a does not do cold boot for secondary CPU */
|
||||
cb_panic:
|
||||
b cb_panic
|
||||
endfunc plat_secondary_cold_boot_setup
|
||||
|
||||
/*
|
||||
* unsigned int plat_is_my_cpu_primary (void);
|
||||
*
|
||||
* Find out whether the current cpu is the primary
|
||||
* cpu.
|
||||
*/
|
||||
func plat_is_my_cpu_primary
|
||||
mrs x0, mpidr_el1
|
||||
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
|
||||
cmp x0, 0x0
|
||||
cset w0, eq
|
||||
ret
|
||||
endfunc plat_is_my_cpu_primary
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SOC_H
|
||||
#define SOC_H
|
||||
|
||||
/* Chassis specific defines - common across SoC's of a particular platform */
|
||||
#include <dcfg_lsch3.h>
|
||||
#include <soc_default_base_addr.h>
|
||||
#include <soc_default_helper_macros.h>
|
||||
|
||||
/*
|
||||
* SVR Definition of LS1028A
|
||||
* (not include major and minor rev)
|
||||
* These info is listed in Table B-6. DCFG differences
|
||||
* between LS1028A and LS1027A of LS1028ARM(Reference Manual)
|
||||
*/
|
||||
#define SVR_LS1017AN 0x870B25
|
||||
#define SVR_LS1017AE 0x870B24
|
||||
#define SVR_LS1018AN 0x870B21
|
||||
#define SVR_LS1018AE 0x870B20
|
||||
#define SVR_LS1027AN 0x870B05
|
||||
#define SVR_LS1027AE 0x870B04
|
||||
#define SVR_LS1028AN 0x870B01
|
||||
#define SVR_LS1028AE 0x870B00
|
||||
|
||||
/* Number of cores in platform */
|
||||
#define PLATFORM_CORE_COUNT 2
|
||||
#define NUMBER_OF_CLUSTERS 1
|
||||
#define CORES_PER_CLUSTER 2
|
||||
|
||||
/* Set to 0 if the clusters are not symmetrical */
|
||||
#define SYMMETRICAL_CLUSTERS 1
|
||||
|
||||
#define NUM_DRAM_REGIONS 3
|
||||
|
||||
#define NXP_DRAM0_ADDR 0x80000000
|
||||
#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2GB */
|
||||
|
||||
#define NXP_DRAM1_ADDR 0x2080000000
|
||||
#define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126G */
|
||||
|
||||
#define NXP_DRAM2_ADDR 0x6000000000
|
||||
#define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */
|
||||
|
||||
/* DRAM0 Size defined in platform_def.h */
|
||||
#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
|
||||
|
||||
/* CCSR space memory Map */
|
||||
#undef NXP_UART_ADDR
|
||||
#define NXP_UART_ADDR 0x021C0500
|
||||
|
||||
#undef NXP_UART1_ADDR
|
||||
#define NXP_UART1_ADDR 0x021C0600
|
||||
|
||||
#undef NXP_WDOG1_TZ_ADDR
|
||||
#define NXP_WDOG1_TZ_ADDR 0x023C0000
|
||||
|
||||
#undef NXP_GICR_ADDR
|
||||
#define NXP_GICR_ADDR 0x06040000
|
||||
|
||||
#undef NXP_GICR_SGI_ADDR
|
||||
#define NXP_GICR_SGI_ADDR 0x06050000
|
||||
|
||||
/* EPU register offsets and values */
|
||||
#define EPU_EPGCR_OFFSET 0x0
|
||||
#define EPU_EPIMCR10_OFFSET 0x128
|
||||
#define EPU_EPCTR10_OFFSET 0xa28
|
||||
#define EPU_EPCCR10_OFFSET 0x828
|
||||
#define EPU_EPCCR10_VAL 0xb2800000
|
||||
#define EPU_EPIMCR10_VAL 0xba000000
|
||||
#define EPU_EPCTR10_VAL 0x0
|
||||
#define EPU_EPGCR_VAL (1 << 31)
|
||||
|
||||
/* PORSR1 */
|
||||
#define PORSR1_RCW_MASK 0x07800000
|
||||
#define PORSR1_RCW_SHIFT 23
|
||||
|
||||
#define SDHC1_VAL 0x8
|
||||
#define SDHC2_VAL 0x9
|
||||
#define I2C1_VAL 0xa
|
||||
#define FLEXSPI_NAND2K_VAL 0xc
|
||||
#define FLEXSPI_NAND4K_VAL 0xd
|
||||
#define FLEXSPI_NOR 0xf
|
||||
|
||||
/*
|
||||
* Required LS standard platform porting definitions
|
||||
* for CCI-400
|
||||
*/
|
||||
#define NXP_CCI_CLUSTER0_SL_IFACE_IX 4
|
||||
|
||||
/* Defines required for using XLAT tables from ARM common code */
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40)
|
||||
|
||||
/* Clock Divisors */
|
||||
#define NXP_PLATFORM_CLK_DIVIDER 1
|
||||
#define NXP_UART_CLK_DIVIDER 2
|
||||
|
||||
/* dcfg register offsets and values */
|
||||
#define DCFG_DEVDISR2_ENETC (1 << 31)
|
||||
|
||||
#define MPIDR_AFFINITY0_MASK 0x00FF
|
||||
#define MPIDR_AFFINITY1_MASK 0xFF00
|
||||
#define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000
|
||||
#define CPUECTLR_INS_PREFETCH_MASK 0x1800000000
|
||||
#define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000
|
||||
#define OSDLR_EL1_DLK_LOCK 0x1
|
||||
#define CNTP_CTL_EL0_EN 0x1
|
||||
#define CNTP_CTL_EL0_IMASK 0x2
|
||||
|
||||
#define SYSTEM_PWR_DOMAINS 1
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
|
||||
NUMBER_OF_CLUSTERS + \
|
||||
SYSTEM_PWR_DOMAINS)
|
||||
|
||||
/* Power state coordination occurs at the system level */
|
||||
#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
|
||||
#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
|
||||
|
||||
/* Local power state for power domains in Run state */
|
||||
#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
|
||||
|
||||
/* define retention state */
|
||||
#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
|
||||
#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
|
||||
|
||||
/* define power-down state */
|
||||
#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
|
||||
#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
|
||||
|
||||
/* One cache line needed for bakery locks on ARM platforms */
|
||||
#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/* CCI slave interfaces */
|
||||
static const int cci_map[] = {
|
||||
NXP_CCI_CLUSTER0_SL_IFACE_IX,
|
||||
};
|
||||
void soc_init_lowlevel(void);
|
||||
void soc_init_percpu(void);
|
||||
void _soc_set_start_addr(unsigned long addr);
|
||||
void _set_platform_security(void);
|
||||
#endif
|
||||
|
||||
#endif /* SOC_H */
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include <string.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
#include <lib/utils.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
#ifdef CONFIG_STATIC_DDR
|
||||
const struct ddr_cfg_regs static_1600 = {
|
||||
.cs[0].config = U(0x80040422),
|
||||
.cs[0].bnds = U(0xFF),
|
||||
.sdram_cfg[0] = U(0xE50C0004),
|
||||
.sdram_cfg[1] = U(0x401100),
|
||||
.timing_cfg[0] = U(0x91550018),
|
||||
.timing_cfg[1] = U(0xBAB40C42),
|
||||
.timing_cfg[2] = U(0x48C111),
|
||||
.timing_cfg[3] = U(0x1111000),
|
||||
.timing_cfg[4] = U(0x2),
|
||||
.timing_cfg[5] = U(0x3401400),
|
||||
.timing_cfg[7] = U(0x23300000),
|
||||
.timing_cfg[8] = U(0x2114600),
|
||||
.sdram_mode[0] = U(0x3010210),
|
||||
.sdram_mode[9] = U(0x4000000),
|
||||
.sdram_mode[8] = U(0x500),
|
||||
.sdram_mode[2] = U(0x10210),
|
||||
.sdram_mode[10] = U(0x400),
|
||||
.sdram_mode[11] = U(0x4000000),
|
||||
.sdram_mode[4] = U(0x10210),
|
||||
.sdram_mode[12] = U(0x400),
|
||||
.sdram_mode[13] = U(0x4000000),
|
||||
.sdram_mode[6] = U(0x10210),
|
||||
.sdram_mode[14] = U(0x400),
|
||||
.sdram_mode[15] = U(0x4000000),
|
||||
.interval = U(0x18600618),
|
||||
.data_init = U(0xdeadbeef),
|
||||
.zq_cntl = U(0x8A090705),
|
||||
.clk_cntl = U(0x2000000),
|
||||
.cdr[0] = U(0x80040000),
|
||||
.cdr[1] = U(0xA181),
|
||||
.wrlvl_cntl[0] = U(0x8675F605),
|
||||
.wrlvl_cntl[1] = U(0x6070700),
|
||||
.wrlvl_cntl[2] = U(0x0000008),
|
||||
.dq_map[0] = U(0x5b65b658),
|
||||
.dq_map[1] = U(0xd96d8000),
|
||||
.dq_map[2] = U(0),
|
||||
.dq_map[3] = U(0x1600000),
|
||||
.debug[28] = U(0x00700046),
|
||||
};
|
||||
|
||||
unsigned long long board_static_ddr(struct ddr_info *priv)
|
||||
{
|
||||
memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
|
||||
return ULL(0x100000000);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static const struct rc_timing rcz[] = {
|
||||
{1600, 8, 5},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_timing ram[] = {
|
||||
{0x1f, rcz, 0x1020200, 0x00000003},
|
||||
};
|
||||
|
||||
int ddr_board_options(struct ddr_info *priv)
|
||||
{
|
||||
int ret;
|
||||
struct memctl_opt *popts = &priv->opt;
|
||||
|
||||
ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
|
||||
if (ret != 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
popts->bstopre = U(0x40); /* precharge value */
|
||||
popts->half_strength_drive_en = 1;
|
||||
popts->cpo_sample = U(0x46);
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
|
||||
DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
|
||||
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
|
||||
|
||||
popts->addr_hash = 1; /* address hashing */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* DDR model number: MT40A1G8SA-075:E */
|
||||
struct dimm_params ddr_raw_timing = {
|
||||
.n_ranks = U(1),
|
||||
.rank_density = ULL(4294967296),
|
||||
.capacity = ULL(4294967296),
|
||||
.primary_sdram_width = U(32),
|
||||
.ec_sdram_width = U(4),
|
||||
.rdimm = U(0),
|
||||
.mirrored_dimm = U(0),
|
||||
.n_row_addr = U(16),
|
||||
.n_col_addr = U(10),
|
||||
.bank_group_bits = U(2),
|
||||
.edc_config = U(2),
|
||||
.burst_lengths_bitmask = U(0x0c),
|
||||
.tckmin_x_ps = 750,
|
||||
.tckmax_ps = 1900,
|
||||
.caslat_x = U(0x0001FFE00),
|
||||
.taa_ps = 13500,
|
||||
.trcd_ps = 13500,
|
||||
.trp_ps = 13500,
|
||||
.tras_ps = 32000,
|
||||
.trc_ps = 45500,
|
||||
.twr_ps = 15000,
|
||||
.trfc1_ps = 350000,
|
||||
.trfc2_ps = 260000,
|
||||
.trfc4_ps = 160000,
|
||||
.tfaw_ps = 21000,
|
||||
.trrds_ps = 3000,
|
||||
.trrdl_ps = 4900,
|
||||
.tccdl_ps = 5000,
|
||||
.refresh_rate_ps = U(7800000),
|
||||
.dq_mapping[0] = U(0x16),
|
||||
.dq_mapping[1] = U(0x36),
|
||||
.dq_mapping[2] = U(0x16),
|
||||
.dq_mapping[3] = U(0x36),
|
||||
.dq_mapping[4] = U(0x16),
|
||||
.dq_mapping[5] = U(0x36),
|
||||
.dq_mapping[6] = U(0x16),
|
||||
.dq_mapping[7] = U(0x36),
|
||||
.dq_mapping[8] = U(0x16),
|
||||
.dq_mapping[9] = U(0x0),
|
||||
.dq_mapping[10] = U(0x0),
|
||||
.dq_mapping[11] = U(0x0),
|
||||
.dq_mapping[12] = U(0x0),
|
||||
.dq_mapping[13] = U(0x0),
|
||||
.dq_mapping[14] = U(0x0),
|
||||
.dq_mapping[15] = U(0x0),
|
||||
.dq_mapping[16] = U(0x0),
|
||||
.dq_mapping[17] = U(0x0),
|
||||
.dq_mapping_ors = U(0),
|
||||
.rc = U(0x1f),
|
||||
};
|
||||
|
||||
int ddr_get_ddr_params(struct dimm_params *pdimm,
|
||||
struct ddr_conf *conf)
|
||||
{
|
||||
static const char dimm_model[] = "Fixed DDR on board";
|
||||
|
||||
conf->dimm_in_use[0] = 1;
|
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
|
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
int64_t init_ddr(void)
|
||||
{
|
||||
struct ddr_info info;
|
||||
struct sysinfo sys;
|
||||
int64_t dram_size;
|
||||
|
||||
zeromem(&sys, sizeof(sys));
|
||||
get_clocks(&sys);
|
||||
debug("platform clock %lu\n", sys.freq_platform);
|
||||
debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
|
||||
|
||||
zeromem(&info, sizeof(struct ddr_info));
|
||||
info.num_ctlrs = 1;
|
||||
info.dimm_on_ctlr = 1;
|
||||
info.clk = get_ddr_freq(&sys, 0);
|
||||
info.ddr[0] = (void *)NXP_DDR_ADDR;
|
||||
|
||||
dram_size = dram_init(&info);
|
||||
|
||||
if (dram_size < 0) {
|
||||
ERROR("DDR init failed.\n");
|
||||
}
|
||||
|
||||
return dram_size;
|
||||
}
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_DEF_H
|
||||
#define PLAT_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <cortex_a72.h>
|
||||
/*
|
||||
* Required without TBBR.
|
||||
* To include the defines for DDR PHY
|
||||
* Images.
|
||||
*/
|
||||
#include <tbbr_img_def.h>
|
||||
|
||||
#include <policy.h>
|
||||
#include <soc.h>
|
||||
|
||||
|
||||
#define NXP_SYSCLK_FREQ 100000000
|
||||
#define NXP_DDRCLK_FREQ 100000000
|
||||
|
||||
/* UART related definition */
|
||||
#define NXP_CONSOLE_ADDR NXP_UART_ADDR
|
||||
#define NXP_CONSOLE_BAUDRATE 115200
|
||||
|
||||
#define NXP_SPD_EEPROM0 0x51
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if defined(IMAGE_BL2)
|
||||
#if defined(TRUSTED_BOARD_BOOT)
|
||||
#define PLATFORM_STACK_SIZE 0x2000
|
||||
#else
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
#elif defined(IMAGE_BL31)
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
/* SD block buffer */
|
||||
#define NXP_SD_BLOCK_BUF_SIZE (0xC000)
|
||||
|
||||
#ifdef SD_BOOT
|
||||
#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
|
||||
- NXP_SD_BLOCK_BUF_SIZE)
|
||||
#else
|
||||
#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
|
||||
#endif
|
||||
#define BL2_TEXT_LIMIT (BL2_LIMIT)
|
||||
|
||||
/* IO defines as needed by IO driver framework */
|
||||
#define MAX_IO_DEVICES 4
|
||||
#define MAX_IO_BLOCK_DEVICES 1
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
#define BL31_WDOG_SEC 89
|
||||
|
||||
/*
|
||||
* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define PLAT_LS_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE)
|
||||
|
||||
/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
|
||||
#define PLAT_LS_G0_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
#endif /* PLAT_DEF_H */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat_common.h>
|
||||
|
||||
#pragma weak board_enable_povdd
|
||||
#pragma weak board_disable_povdd
|
||||
|
||||
bool board_enable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
bool board_disable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#
|
||||
# Copyright 2020-2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# Board-specific build parameters
|
||||
BOOT_MODE ?= flexspi_nor
|
||||
BOARD := ls1028ardb
|
||||
POVDD_ENABLE := no
|
||||
WARM_BOOT := no
|
||||
|
||||
# DDR build parameters
|
||||
NUM_OF_DDRC := 1
|
||||
CONFIG_DDR_NODIMM := 1
|
||||
DDR_ECC_EN := yes
|
||||
|
||||
# On-board flash
|
||||
FLASH_TYPE := MT35XU02G
|
||||
XSPI_FLASH_SZ := 0x10000000
|
||||
|
||||
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c \
|
||||
${BOARD_PATH}/platform.c
|
||||
|
||||
SUPPORTED_BOOT_MODE := flexspi_nor \
|
||||
sd \
|
||||
emmc
|
||||
|
||||
# Add platform board build info
|
||||
include plat/nxp/common/plat_make_helper/plat_common_def.mk
|
||||
|
||||
# Add SoC build info
|
||||
include plat/nxp/soc-ls1028a/soc.mk
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright 2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <plat_def.h>
|
||||
#include <plat_default_def.h>
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef POLICY_H
|
||||
#define POLICY_H
|
||||
|
||||
/*
|
||||
* Set this to 0x0 to leave the default SMMU page size in sACR
|
||||
* Set this to 0x1 to change the SMMU page size to 64K
|
||||
*/
|
||||
#define POLICY_SMMU_PAGESZ_64K 0x1
|
||||
|
||||
#endif /* POLICY_H */
|
||||
|
|
@ -0,0 +1,420 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <endian.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <caam.h>
|
||||
#include <cassert.h>
|
||||
#include <cci.h>
|
||||
#include <common/debug.h>
|
||||
#include <dcfg.h>
|
||||
#include <i2c.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <ls_interconnect.h>
|
||||
#include <mmio.h>
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
#include <nxp_smmu.h>
|
||||
#endif
|
||||
#include <nxp_timer.h>
|
||||
#ifdef CONFIG_OCRAM_ECC_EN
|
||||
#include <ocram.h>
|
||||
#endif
|
||||
#include <plat_console.h>
|
||||
#include <plat_gic.h>
|
||||
#include <plat_tzc400.h>
|
||||
#include <pmu.h>
|
||||
#include <scfg.h>
|
||||
#if defined(NXP_SFP_ENABLED)
|
||||
#include <sfp.h>
|
||||
#endif
|
||||
|
||||
#include <errata.h>
|
||||
#include "plat_common.h"
|
||||
#include "platform_def.h"
|
||||
#include "soc.h"
|
||||
|
||||
static dcfg_init_info_t dcfg_init_data = {
|
||||
.g_nxp_dcfg_addr = NXP_DCFG_ADDR,
|
||||
.nxp_sysclk_freq = NXP_SYSCLK_FREQ,
|
||||
.nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
|
||||
.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
|
||||
};
|
||||
|
||||
static struct soc_type soc_list[] = {
|
||||
SOC_ENTRY(LS1017AN, LS1017AN, 1, 1),
|
||||
SOC_ENTRY(LS1017AE, LS1017AE, 1, 1),
|
||||
SOC_ENTRY(LS1018AN, LS1018AN, 1, 1),
|
||||
SOC_ENTRY(LS1018AE, LS1018AE, 1, 1),
|
||||
SOC_ENTRY(LS1027AN, LS1027AN, 1, 2),
|
||||
SOC_ENTRY(LS1027AE, LS1027AE, 1, 2),
|
||||
SOC_ENTRY(LS1028AN, LS1028AN, 1, 2),
|
||||
SOC_ENTRY(LS1028AE, LS1028AE, 1, 2),
|
||||
};
|
||||
|
||||
CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
|
||||
assert_invalid_ls1028a_cluster_count);
|
||||
|
||||
/*
|
||||
* Function returns the base counter frequency
|
||||
* after reading the first entry at CNTFID0 (0x20 offset).
|
||||
*
|
||||
* Function is used by:
|
||||
* 1. ARM common code for PSCI management.
|
||||
* 2. ARM Generic Timer init.
|
||||
*
|
||||
*/
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
unsigned int counter_base_frequency;
|
||||
/*
|
||||
* Below register specifies the base frequency of the system counter.
|
||||
* As per NXP Board Manuals:
|
||||
* The system counter always works with SYS_REF_CLK/4 frequency clock.
|
||||
*/
|
||||
counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF);
|
||||
|
||||
return counter_base_frequency;
|
||||
}
|
||||
|
||||
#ifdef IMAGE_BL2
|
||||
void soc_preload_setup(void)
|
||||
{
|
||||
}
|
||||
|
||||
void soc_early_init(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
#ifdef CONFIG_OCRAM_ECC_EN
|
||||
ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
|
||||
#endif
|
||||
dcfg_init(&dcfg_init_data);
|
||||
enable_timer_base_to_cluster(NXP_PMU_ADDR);
|
||||
enable_core_tb(NXP_PMU_ADDR);
|
||||
dram_regions_info_t *dram_regions_info = get_dram_regions_info();
|
||||
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
gpio_init(&gpio_init_data);
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
#endif
|
||||
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
enum boot_device dev = get_boot_dev();
|
||||
/*
|
||||
* Mark the buffer for SD in OCRAM as non secure.
|
||||
* The buffer is assumed to be at end of OCRAM for
|
||||
* the logic below to calculate TZPC programming
|
||||
*/
|
||||
if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) {
|
||||
/*
|
||||
* Calculate the region in OCRAM which is secure
|
||||
* The buffer for SD needs to be marked non-secure
|
||||
* to allow SD to do DMA operations on it
|
||||
*/
|
||||
uint32_t secure_region = (NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE);
|
||||
uint32_t mask = secure_region/TZPC_BLOCK_SIZE;
|
||||
|
||||
mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask);
|
||||
|
||||
/* Add the entry for buffer in MMU Table */
|
||||
mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR,
|
||||
NXP_SD_BLOCK_BUF_SIZE, MT_DEVICE | MT_RW | MT_NS);
|
||||
}
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
uint32_t mode;
|
||||
|
||||
sfp_init(NXP_SFP_ADDR);
|
||||
|
||||
/*
|
||||
* For secure boot disable SMMU.
|
||||
* Later when platform security policy comes in picture,
|
||||
* this might get modified based on the policy
|
||||
*/
|
||||
if (check_boot_mode_secure(&mode) == true) {
|
||||
bypass_smmu(NXP_SMMU_ADDR);
|
||||
}
|
||||
|
||||
/*
|
||||
* For Mbedtls currently crypto is not supported via CAAM
|
||||
* enable it when that support is there. In tbbr.mk
|
||||
* the CAAM_INTEG is set as 0.
|
||||
*/
|
||||
#ifndef MBEDTLS_X509
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled()) {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
} else {
|
||||
INFO("SEC is disabled.\n");
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Set eDDRTQ for DDR performance */
|
||||
scfg_setbits32((void *)(NXP_SCFG_ADDR + 0x210), 0x1f1f1f1f);
|
||||
|
||||
soc_errata();
|
||||
|
||||
/*
|
||||
* Initialize Interconnect for this cluster during cold boot.
|
||||
* No need for locks as no other CPU is active.
|
||||
*/
|
||||
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
|
||||
|
||||
/*
|
||||
* Enable Interconnect coherency for the primary CPU's cluster.
|
||||
*/
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
plat_ls_interconnect_enter_coherency(num_clusters);
|
||||
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
i2c_init(NXP_I2C_ADDR);
|
||||
dram_regions_info->total_dram_size = init_ddr();
|
||||
}
|
||||
|
||||
void soc_bl2_prepare_exit(void)
|
||||
{
|
||||
#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
|
||||
set_sfp_wr_disable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the boot device based on RCW_SRC
|
||||
*/
|
||||
enum boot_device get_boot_dev(void)
|
||||
{
|
||||
enum boot_device src = BOOT_DEVICE_NONE;
|
||||
uint32_t porsr1;
|
||||
uint32_t rcw_src;
|
||||
|
||||
porsr1 = read_reg_porsr1();
|
||||
|
||||
rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
|
||||
switch (rcw_src) {
|
||||
case FLEXSPI_NOR:
|
||||
src = BOOT_DEVICE_FLEXSPI_NOR;
|
||||
INFO("RCW BOOT SRC is FLEXSPI NOR\n");
|
||||
break;
|
||||
case FLEXSPI_NAND2K_VAL:
|
||||
case FLEXSPI_NAND4K_VAL:
|
||||
INFO("RCW BOOT SRC is FLEXSPI NAND\n");
|
||||
src = BOOT_DEVICE_FLEXSPI_NAND;
|
||||
break;
|
||||
case SDHC1_VAL:
|
||||
src = BOOT_DEVICE_EMMC;
|
||||
INFO("RCW BOOT SRC is SD\n");
|
||||
break;
|
||||
case SDHC2_VAL:
|
||||
src = BOOT_DEVICE_SDHC2_EMMC;
|
||||
INFO("RCW BOOT SRC is EMMC\n");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return src;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function sets up access permissions on memory regions
|
||||
****************************************************************************/
|
||||
void soc_mem_access(void)
|
||||
{
|
||||
dram_regions_info_t *info_dram_regions = get_dram_regions_info();
|
||||
struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
|
||||
int dram_idx = 0;
|
||||
/* index 0 is reserved for region-0 */
|
||||
int index = 1;
|
||||
|
||||
for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions;
|
||||
dram_idx++) {
|
||||
if (info_dram_regions->region[dram_idx].size == 0) {
|
||||
ERROR("DDR init failure, or");
|
||||
ERROR("DRAM regions not populated correctly.\n");
|
||||
break;
|
||||
}
|
||||
|
||||
index = populate_tzc400_reg_list(tzc400_reg_list,
|
||||
dram_idx, index,
|
||||
info_dram_regions->region[dram_idx].addr,
|
||||
info_dram_regions->region[dram_idx].size,
|
||||
NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
|
||||
}
|
||||
|
||||
mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2];
|
||||
/*
|
||||
* This function dynamically constructs the topology according to
|
||||
* SoC Flavor and returns it.
|
||||
*/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
unsigned int i;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
/*
|
||||
* The highest level is the system level. The next level is constituted
|
||||
* by clusters and then cores in clusters.
|
||||
*/
|
||||
_power_domain_tree_desc[0] = 1;
|
||||
_power_domain_tree_desc[1] = num_clusters;
|
||||
|
||||
for (i = 0; i < _power_domain_tree_desc[1]; i++)
|
||||
_power_domain_tree_desc[i + 2] = cores_per_cluster;
|
||||
|
||||
return _power_domain_tree_desc;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the core count within the cluster corresponding to
|
||||
* `mpidr`.
|
||||
*/
|
||||
unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
return num_clusters;
|
||||
}
|
||||
|
||||
void soc_early_platform_setup2(void)
|
||||
{
|
||||
dcfg_init(&dcfg_init_data);
|
||||
/* Initialize system level generic timer for Socs */
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
}
|
||||
|
||||
void soc_platform_setup(void)
|
||||
{
|
||||
/* Initialize the GIC driver, cpu and distributor interfaces */
|
||||
static uintptr_t target_mask_array[PLATFORM_CORE_COUNT];
|
||||
static interrupt_prop_t ls_interrupt_props[] = {
|
||||
PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S),
|
||||
PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0)
|
||||
};
|
||||
|
||||
plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR,
|
||||
PLATFORM_CORE_COUNT,
|
||||
ls_interrupt_props,
|
||||
ARRAY_SIZE(ls_interrupt_props),
|
||||
target_mask_array,
|
||||
plat_core_pos);
|
||||
|
||||
plat_ls_gic_init();
|
||||
enable_init_timer();
|
||||
}
|
||||
|
||||
/* This function initializes the soc from the BL31 module */
|
||||
void soc_init(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
|
||||
/* Low-level init of the soc */
|
||||
soc_init_lowlevel();
|
||||
_init_global_data();
|
||||
soc_init_percpu();
|
||||
_initialize_psci();
|
||||
|
||||
/*
|
||||
* Initialize Interconnect for this cluster during cold boot.
|
||||
* No need for locks as no other CPU is active.
|
||||
*/
|
||||
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
|
||||
|
||||
/* Enable Interconnect coherency for the primary CPU's cluster. */
|
||||
plat_ls_interconnect_enter_coherency(num_clusters);
|
||||
|
||||
/* Set platform security policies */
|
||||
_set_platform_security();
|
||||
|
||||
/* Init SEC Engine which will be used by SiP */
|
||||
if (is_sec_enabled()) {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
} else {
|
||||
INFO("SEC is disabled.\n");
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef NXP_WDOG_RESTART
|
||||
static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags,
|
||||
void *handle, void *cookie)
|
||||
{
|
||||
uint8_t data = WDOG_RESET_FLAG;
|
||||
|
||||
wr_nv_app_data(WDT_RESET_FLAG_OFFSET,
|
||||
(uint8_t *)&data, sizeof(data));
|
||||
|
||||
mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void soc_runtime_setup(void)
|
||||
{
|
||||
#ifdef NXP_WDOG_RESTART
|
||||
request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* This function returns the total number of cores in the SoC. */
|
||||
unsigned int get_tot_num_cores(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
return (num_clusters * cores_per_cluster);
|
||||
}
|
||||
|
||||
/* This function returns the PMU IDLE Cluster mask. */
|
||||
unsigned int get_pmu_idle_cluster_mask(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
return ((1 << num_clusters) - 2);
|
||||
}
|
||||
|
||||
/* This function returns the PMU Flush Cluster mask. */
|
||||
unsigned int get_pmu_flush_cluster_mask(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
return ((1 << num_clusters) - 2);
|
||||
}
|
||||
|
||||
/* This function returns the PMU idle core mask. */
|
||||
unsigned int get_pmu_idle_core_mask(void)
|
||||
{
|
||||
return ((1 << get_tot_num_cores()) - 2);
|
||||
}
|
||||
|
||||
/* Function to return the SoC SYS CLK */
|
||||
unsigned int get_sys_clk(void)
|
||||
{
|
||||
return NXP_SYSCLK_FREQ;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
#
|
||||
# Copyright 2018-2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# This file contains the basic architecture definitions that drive the build
|
||||
#
|
||||
# -----------------------------------------------------------------------------
|
||||
|
||||
CORE_TYPE := a72
|
||||
|
||||
CACHE_LINE := 6
|
||||
|
||||
# Set to GIC400 or GIC500
|
||||
GIC := GIC500
|
||||
|
||||
# Set to CCI400 or CCN504 or CCN508
|
||||
INTERCONNECT := CCI400
|
||||
|
||||
# Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
|
||||
CHASSIS := 3_2
|
||||
|
||||
# TZC used is TZC380 or TZC400
|
||||
TZC_ID := TZC400
|
||||
|
||||
# CONSOLE is NS16550 or PL011
|
||||
CONSOLE := NS16550
|
||||
|
||||
# DDR PHY generation to be used
|
||||
PLAT_DDR_PHY := PHY_GEN1
|
||||
|
||||
PHYS_SYS := 64
|
||||
|
||||
# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
|
||||
# Input to CST create_hdr_esbc tool
|
||||
CSF_HDR_SZ := 0x3000
|
||||
|
||||
# In IMAGE_BL2, compile time flag for handling Cache coherency
|
||||
# with CAAM for BL2 running from OCRAM
|
||||
SEC_MEM_NON_COHERENT := yes
|
||||
|
||||
# OCRAM MAP for BL2
|
||||
# Before BL2
|
||||
# 0x18000000 - 0x18009fff -> Used by ROM code
|
||||
# 0x1800a000 - 0x1800dfff -> CSF header for BL2
|
||||
# For FlexSFlexSPI boot
|
||||
# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary
|
||||
# For SD boot
|
||||
# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary
|
||||
# 0x18030000 - 0x18040000 -> Reserved for SD buffer
|
||||
OCRAM_START_ADDR := 0x18000000
|
||||
OCRAM_SIZE := 0x40000
|
||||
|
||||
# Area of OCRAM reserved by ROM code
|
||||
NXP_ROM_RSVD := 0xa000
|
||||
|
||||
# Location of BL2 on OCRAM
|
||||
BL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))
|
||||
|
||||
# Covert to HEX to be used by create_pbl.mk
|
||||
BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
|
||||
|
||||
# BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD)
|
||||
# This value BL2_HDR_LOC + CSF_HDR_SZ should not
|
||||
# overalp with BL2_BASE
|
||||
# Input to CST create_hdr_isbc tool
|
||||
BL2_HDR_LOC := 0x1800A000
|
||||
|
||||
# SoC ERRATAS to be enabled
|
||||
ERRATA_SOC_A008850 := 1
|
||||
|
||||
ERRATA_DDR_A009803 := 1
|
||||
ERRATA_DDR_A009942 := 1
|
||||
ERRATA_DDR_A010165 := 1
|
||||
|
||||
# Enable dynamic memory mapping
|
||||
PLAT_XLAT_TABLES_DYNAMIC := 1
|
||||
|
||||
# Define Endianness of each module
|
||||
NXP_GUR_ENDIANNESS := LE
|
||||
NXP_DDR_ENDIANNESS := LE
|
||||
NXP_SEC_ENDIANNESS := LE
|
||||
NXP_SFP_ENDIANNESS := LE
|
||||
NXP_SNVS_ENDIANNESS := LE
|
||||
NXP_ESDHC_ENDIANNESS := LE
|
||||
NXP_QSPI_ENDIANNESS := LE
|
||||
NXP_FSPI_ENDIANNESS := LE
|
||||
|
||||
NXP_SFP_VER := 3_4
|
||||
|
||||
# OCRAM ECC Enabled
|
||||
OCRAM_ECC_EN := yes
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
#
|
||||
# Copyright 2020-2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# SoC-specific build parameters
|
||||
SOC := ls1028a
|
||||
PLAT_PATH := plat/nxp
|
||||
PLAT_COMMON_PATH := plat/nxp/common
|
||||
PLAT_DRIVERS_PATH := drivers/nxp
|
||||
PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC}
|
||||
BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD}
|
||||
|
||||
# Get SoC-specific definitions
|
||||
include ${PLAT_SOC_PATH}/soc.def
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
|
||||
|
||||
ifeq (${TRUSTED_BOARD_BOOT},1)
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
|
||||
SECURE_BOOT := yes
|
||||
endif
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
|
||||
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
|
||||
|
||||
# Selecting PSCI & SIP_SVC support
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
|
||||
|
||||
PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
|
||||
-I${BOARD_PATH}\
|
||||
-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
|
||||
-I${PLAT_SOC_PATH}/include\
|
||||
-I${PLAT_COMMON_PATH}/soc_errata
|
||||
|
||||
ifeq (${SECURE_BOOT},yes)
|
||||
include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
|
||||
endif
|
||||
|
||||
ifeq ($(WARM_BOOT),yes)
|
||||
include ${PLAT_COMMON_PATH}/warm_reset/warm_reset.mk
|
||||
endif
|
||||
|
||||
ifeq (${NXP_NV_SW_MAINT_LAST_EXEC_DATA}, yes)
|
||||
include ${PLAT_COMMON_PATH}/nv_storage/nv_storage.mk
|
||||
endif
|
||||
|
||||
ifeq (${PSCI_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/psci/psci.mk
|
||||
endif
|
||||
|
||||
ifeq (${SIPSVC_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
|
||||
endif
|
||||
|
||||
ifeq (${DDR_FIP_IO_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/fip_handler/ddr_fip/ddr_fip_io.mk
|
||||
endif
|
||||
|
||||
# For fuse-fip & fuse-programming
|
||||
ifeq (${FUSE_PROG}, 1)
|
||||
include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
|
||||
endif
|
||||
|
||||
ifeq (${IMG_LOADR_NEEDED},yes)
|
||||
include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
|
||||
endif
|
||||
|
||||
# Adding source files for the above selected drivers.
|
||||
include ${PLAT_DRIVERS_PATH}/drivers.mk
|
||||
|
||||
# Adding SoC specific files
|
||||
include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
|
||||
|
||||
PLAT_INCLUDES += ${NV_STORAGE_INCLUDES}\
|
||||
${WARM_RST_INCLUDES}
|
||||
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
|
||||
${WARM_RST_BL31_SOURCES}\
|
||||
${PSCI_SOURCES}\
|
||||
${SIPSVC_SOURCES}\
|
||||
${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
|
||||
${PLAT_SOC_PATH}/aarch64/${SOC}_helpers.S\
|
||||
${NV_STORAGE_SOURCES}\
|
||||
${WARM_RST_BL_COMM_SOURCES}\
|
||||
${PLAT_SOC_PATH}/soc.c
|
||||
|
||||
ifeq (${TEST_BL31}, 1)
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S \
|
||||
${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
|
||||
endif
|
||||
|
||||
BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
|
||||
${TBBR_SOURCES}\
|
||||
${FUSE_SOURCES}
|
||||
|
||||
# Adding TFA setup files
|
||||
include ${PLAT_PATH}/common/setup/common.mk
|
||||
Loading…
Reference in New Issue