Merge "stm32mp1: shared resources: peripheral registering" into integration
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ac6b3b285a
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@ -9,13 +9,22 @@
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#include <stdbool.h>
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#include <stdbool.h>
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#ifdef STM32MP_SHARED_RESOURCES
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enum stm32mp_shres;
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/* Return true if @clock_id is shared by secure and non-secure worlds */
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/* Return true if @clock_id is shared by secure and non-secure worlds */
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bool stm32mp_nsec_can_access_clock(unsigned long clock_id);
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bool stm32mp_nsec_can_access_clock(unsigned long clock_id);
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/* Return true if and only if @reset_id relates to a non-secure peripheral */
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/* Return true if and only if @reset_id relates to a non-secure peripheral */
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bool stm32mp_nsec_can_access_reset(unsigned int reset_id);
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bool stm32mp_nsec_can_access_reset(unsigned int reset_id);
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/* Register a shared resource assigned to the secure world */
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void stm32mp_register_secure_periph(enum stm32mp_shres id);
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/* Register a shared resource assigned to the non-secure world */
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void stm32mp_register_non_secure_periph(enum stm32mp_shres id);
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/* Consolidate peripheral states and lock against new peripheral registering */
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/* Consolidate peripheral states and lock against new peripheral registering */
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void stm32mp_lock_periph_registering(void);
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void stm32mp_lock_periph_registering(void);
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#endif /* STM32MP_SHARED_RESOURCES */
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#endif /* STM32MP_SHARED_RESOURCES_H */
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#endif /* STM32MP_SHARED_RESOURCES_H */
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@ -135,6 +135,104 @@ static unsigned int get_gpioz_nbpin(void)
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return get_gpio_nbpin(GPIO_BANK_Z);
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return get_gpio_nbpin(GPIO_BANK_Z);
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}
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}
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static void register_periph(enum stm32mp_shres id, unsigned int state)
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{
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assert((id < STM32MP1_SHRES_COUNT) &&
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((state == SHRES_SECURE) || (state == SHRES_NON_SECURE)));
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if (registering_locked) {
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if (shres_state[id] == state) {
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return;
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}
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panic();
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}
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if ((shres_state[id] != SHRES_UNREGISTERED) &&
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(shres_state[id] != state)) {
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VERBOSE("Cannot change %s from %s to %s\n",
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shres2str_id(id),
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shres2str_state(shres_state[id]),
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shres2str_state(state));
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panic();
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}
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if (shres_state[id] == SHRES_UNREGISTERED) {
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VERBOSE("Register %s as %s\n",
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shres2str_id(id), shres2str_state(state));
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}
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if ((id >= STM32MP1_SHRES_GPIOZ(0)) &&
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(id <= STM32MP1_SHRES_GPIOZ(7)) &&
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((id - STM32MP1_SHRES_GPIOZ(0)) >= get_gpioz_nbpin())) {
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ERROR("Invalid GPIO pin %u, %u pin(s) available\n",
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id - STM32MP1_SHRES_GPIOZ(0), get_gpioz_nbpin());
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panic();
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}
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shres_state[id] = (uint8_t)state;
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/* Explore clock tree to lock dependencies */
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if (state == SHRES_SECURE) {
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enum stm32mp_shres clock_res_id;
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switch (id) {
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case STM32MP1_SHRES_GPIOZ(0):
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case STM32MP1_SHRES_GPIOZ(1):
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case STM32MP1_SHRES_GPIOZ(2):
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case STM32MP1_SHRES_GPIOZ(3):
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case STM32MP1_SHRES_GPIOZ(4):
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case STM32MP1_SHRES_GPIOZ(5):
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case STM32MP1_SHRES_GPIOZ(6):
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case STM32MP1_SHRES_GPIOZ(7):
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clock_res_id = GPIOZ;
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break;
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case STM32MP1_SHRES_IWDG1:
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clock_res_id = IWDG1;
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break;
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case STM32MP1_SHRES_USART1:
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clock_res_id = USART1_K;
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break;
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case STM32MP1_SHRES_SPI6:
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clock_res_id = SPI6_K;
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break;
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case STM32MP1_SHRES_I2C4:
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clock_res_id = I2C4_K;
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break;
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case STM32MP1_SHRES_RNG1:
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clock_res_id = RNG1_K;
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break;
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case STM32MP1_SHRES_HASH1:
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clock_res_id = HASH1;
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break;
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case STM32MP1_SHRES_CRYP1:
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clock_res_id = CRYP1;
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break;
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case STM32MP1_SHRES_I2C6:
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clock_res_id = I2C6_K;
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break;
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case STM32MP1_SHRES_RTC:
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clock_res_id = RTC;
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break;
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default:
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/* No clock resource dependency */
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return;
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}
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stm32mp1_register_clock_parents_secure(clock_res_id);
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}
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}
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/* Register resource by ID */
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void stm32mp_register_secure_periph(enum stm32mp_shres id)
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{
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register_periph(id, SHRES_SECURE);
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}
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void stm32mp_register_non_secure_periph(enum stm32mp_shres id)
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{
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register_periph(id, SHRES_NON_SECURE);
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}
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/* Currently allow full access by non-secure to platform clock services */
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/* Currently allow full access by non-secure to platform clock services */
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bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
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bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
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{
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{
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