andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

rockchip: Change the callback implement of power domain for rk3368 

Change-Id: I6d39b4cac9b34b1f841e9bbddaf9c49785ba0c5e
Signed-off-by: tony.xie <tony.xie@rock-chips.com>
This commit is contained in:
tony.xie 2017-03-03 16:22:12 +08:00
parent f32ab4445a
commit ad2c05671d
3 changed files with 5 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
plat/rockchip/rk3368/drivers/pmu/pmu.c
View File

@ -343,7 +343,7 @@ static void nonboot_cpus_off(void)
}
}
static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
{
uint32_t cpu, cluster;
uint32_t cpuon_id;
@ -375,12 +375,12 @@ static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint)
return 0;
}
static int cores_pwr_domain_on_finish(void)
int rockchip_soc_cores_pwr_dm_on_finish(void)
{
return 0;
}
static int sys_pwr_domain_resume(void)
int rockchip_soc_sys_pwr_dm_resume(void)
{
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
(COLD_BOOT_BASE >> CPU_BOOT_ADDR_ALIGN) |
@ -394,7 +394,7 @@ static int sys_pwr_domain_resume(void)
return 0;
}
static int sys_pwr_domain_suspend(void)
int rockchip_soc_sys_pwr_dm_suspend(void)
{
nonboot_cpus_off();
pmu_set_sleep_mode();
@ -404,20 +404,10 @@ static int sys_pwr_domain_suspend(void)
return 0;
}
static struct rockchip_pm_ops_cb pm_ops = {
.cores_pwr_dm_on = cores_pwr_domain_on,
.cores_pwr_dm_on_finish = cores_pwr_domain_on_finish,
.sys_pwr_dm_suspend = sys_pwr_domain_suspend,
.sys_pwr_dm_resume = sys_pwr_domain_resume,
.sys_gbl_soft_reset = soc_sys_global_soft_reset,
};
void plat_rockchip_pmu_init(void)
{
uint32_t cpu;
plat_setup_rockchip_pm_ops(&pm_ops);
/* register requires 32bits mode, switch it to 32 bits */
cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot;

2
plat/rockchip/rk3368/drivers/soc/soc.c
View File

@ -198,7 +198,7 @@ void pm_plls_resume(void)
plls_con[NPLL_ID][3] | PLLS_MODE_WMASK);
}
void __dead2 soc_sys_global_soft_reset(void)
void __dead2 rockchip_soc_soft_reset(void)
{
uint32_t temp_val;

1
plat/rockchip/rk3368/drivers/soc/soc.h
View File

@ -157,7 +157,6 @@ enum plls_id {
#define regs_updata_bit_clr(addr, shift) \
regs_updata_bits((addr), 0x0, 0x1, (shift))
void __dead2 soc_sys_global_soft_reset(void);
void regs_updata_bits(uintptr_t addr, uint32_t val,
uint32_t mask, uint32_t shift);
void soc_sleep_config(void);