Merge pull request #772 from davidcunado-arm/dc/reset_debug_reg
Reset EL2 and EL3 configurable controls
This commit is contained in:
commit
ad64ab28b1
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@ -67,14 +67,6 @@
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orr r0, r0, #SCR_SIF_BIT
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orr r0, r0, #SCR_SIF_BIT
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stcopr r0, SCR
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stcopr r0, SCR
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/* -----------------------------------------------------------------
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* Reset those registers that may have architecturally unknown reset
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* values
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* -----------------------------------------------------------------
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*/
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mov r0, #0
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stcopr r0, SDCR
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/* -----------------------------------------------------
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/* -----------------------------------------------------
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* Enable the Asynchronous data abort now that the
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* Enable the Asynchronous data abort now that the
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* exception vectors have been setup.
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* exception vectors have been setup.
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@ -382,8 +382,8 @@
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/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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#define HDCR p15, 4, c1, c1, 1
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#define HDCR p15, 4, c1, c1, 1
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#define SDCR p15, 0, c1, c3, 1
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#define PMCR p15, 0, c9, c12, 0
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#define PMCR p15, 0, c9, c12, 0
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#define CNTHP_CTL p15, 4, c14, c2, 1
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/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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#define ICC_IAR1 p15, 0, c12, c12, 0
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#define ICC_IAR1 p15, 0, c12, c12, 0
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@ -250,6 +250,7 @@ DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
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DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
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DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
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DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
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DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
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DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
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DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
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DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
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/*
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/*
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@ -280,6 +280,8 @@ DEFINE_SYSREG_READ_FUNC(isr_el1)
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DEFINE_SYSREG_READ_FUNC(ctr_el0)
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DEFINE_SYSREG_READ_FUNC(ctr_el0)
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DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
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DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
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DEFINE_SYSREG_RW_FUNCS(hstr_el2)
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DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
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DEFINE_SYSREG_READ_FUNC(pmcr_el0)
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DEFINE_SYSREG_READ_FUNC(pmcr_el0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
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@ -243,6 +243,12 @@ void cm_prepare_el3_exit(uint32_t security_state)
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* (5 bits) and HPMN is at offset zero within HDCR.
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* (5 bits) and HPMN is at offset zero within HDCR.
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*/
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*/
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write_hdcr((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT);
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write_hdcr((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT);
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/*
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* Reset CNTHP_CTL to disable the EL2 physical timer and
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* therefore prevent timer interrupts.
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*/
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write_cnthp_ctl(0);
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isb();
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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write_scr(read_scr() & ~SCR_NS_BIT);
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@ -269,6 +269,18 @@ void cm_prepare_el3_exit(uint32_t security_state)
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*/
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*/
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write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS)
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write_mdcr_el2((read_pmcr_el0() & PMCR_EL0_N_BITS)
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>> PMCR_EL0_N_SHIFT);
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>> PMCR_EL0_N_SHIFT);
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/*
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* Avoid unexpected traps of non-secure access to
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* certain system registers at EL1 or lower where
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* HSTR_EL2 is not completely reset to zero by the
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* hardware - zero the entire register.
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*/
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write_hstr_el2(0);
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/*
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* Reset CNTHP_CTL_EL2 to disable the EL2 physical timer
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* and therefore prevent timer interrupts.
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*/
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write_cnthp_ctl_el2(0);
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}
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}
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}
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}
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