plat: tc0: Enable SPMC execution at S-EL2
This patch enables SPMC execution at S-EL2 by adding below changes
- Map TC0_MAP_TZC_DRAM1 for loading SPMC
- Add details of cactus test secure partitions
- Adds tc0 spmc manifest file with details on secure partitions
- Inlcude TOS_FW_CONFIG when SPM is spmd
- Increases bl2 image size
SPMC at S-EL2 is only enabled when build with SPD=spmd.
Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
This commit is contained in:
Arunachalam Ganapathy
Manish Pandey
parent
a3ecbb3553
commit
b0d127515a
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@ -14,10 +14,16 @@
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tb_fw-config {
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load-address = <0x0 0x4001300>;
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max-size = <0x200>;
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max-size = <0x400>;
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id = <TB_FW_CONFIG_ID>;
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};
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tos_fw-config {
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load-address = <0x0 0x04001700>;
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max-size = <0x1000>;
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id = <TOS_FW_CONFIG_ID>;
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};
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hw-config {
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load-address = <0x0 0x83000000>;
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max-size = <0x01000000>;
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@ -0,0 +1,93 @@
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/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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compatible = "arm,ffa-core-manifest-1.0";
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#address-cells = <2>;
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#size-cells = <1>;
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attribute {
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spmc_id = <0x8000>;
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maj_ver = <0x1>;
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min_ver = <0x0>;
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exec_state = <0x0>;
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load_address = <0x0 0xfd000000>;
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entrypoint = <0x0 0xfd000000>;
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binary_size = <0x80000>;
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};
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chosen {
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linux,initrd-start = <0>;
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linux,initrd-end = <0>;
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};
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hypervisor {
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compatible = "hafnium,hafnium";
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vm1 {
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is_ffa_partition;
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debug_name = "cactus-primary";
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load_address = <0xfe000000>;
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};
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vm2 {
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is_ffa_partition;
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debug_name = "cactus-secondary";
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load_address = <0xfe100000>;
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vcpu_count = <4>;
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mem_size = <1048576>;
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};
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vm3 {
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is_ffa_partition;
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debug_name = "cactus-tertiary";
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load_address = <0xfe200000>;
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vcpu_count = <4>;
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mem_size = <1048576>;
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};
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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/*
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* SPM(Hafnium) requires secondary cpu nodes are declared in
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* descending order
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*/
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CPU3:cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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};
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CPU2:cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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};
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CPU1:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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};
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/* 32MB of TC0_TZC_DRAM1_BASE */
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memory@fd000000 {
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device_type = "memory";
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reg = <0x0 0xfd000000 0x2000000>;
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};
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};
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@ -24,4 +24,24 @@
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mbedtls_heap_addr = <0x0 0x0>;
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mbedtls_heap_size = <0x0>;
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};
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secure-partitions {
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compatible = "arm,sp";
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cactus-primary {
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uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>;
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load-address = <0xfe000000>;
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owner = "SiP";
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};
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cactus-secondary {
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uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>;
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load-address = <0xfe100000>;
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owner = "Plat";
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};
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cactus-tertiary {
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uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>;
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load-address = <0xfe200000>;
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};
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};
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};
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@ -55,6 +55,14 @@
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TC0_TZC_DRAM1_BASE, \
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TC0_TZC_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* Max size of SPMC is 2MB for tc0. With SPMD enabled this value corresponds to
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* max size of BL32 image.
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*/
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#if defined(SPD_spmd)
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#define PLAT_ARM_SPMC_BASE TC0_TZC_DRAM1_BASE
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#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
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#endif
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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@ -106,7 +114,7 @@
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#if TRUSTED_BOARD_BOOT
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# define PLAT_ARM_MAX_BL2_SIZE 0x1E000
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0x11000
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# define PLAT_ARM_MAX_BL2_SIZE 0x14000
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#endif
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/*
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@ -241,4 +249,7 @@
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#define PLAT_ARM_TZC_NS_DEV_ACCESS \
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(TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
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/* virtual address used by dynamic mem_protect for chunk_base */
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#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
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#endif /* PLATFORM_DEF_H */
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@ -85,6 +85,14 @@ $(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
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# Add the TB_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
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ifeq (${SPD},spmd)
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FDT_SOURCES += ${TC0_BASE}/fdts/${PLAT}_spmc_manifest.dts
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TC0_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_spmc_manifest.dtb
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# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
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$(eval $(call TOOL_ADD_PAYLOAD,${TC0_TOS_FW_CONFIG},--tos-fw-config,${TC0_TOS_FW_CONFIG}))
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endif
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#Device tree
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TC0_HW_CONFIG_DTS := fdts/tc0.dts
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TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
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@ -39,6 +39,9 @@ const mmap_region_t plat_arm_mmap[] = {
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TC0_FLASH0_RO,
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TC0_MAP_DEVICE,
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TC0_MAP_NS_DRAM1,
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#if defined(SPD_spmd)
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TC0_MAP_TZC_DRAM1,
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#endif
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#if ARM_BL31_IN_DRAM
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ARM_MAP_BL31_SEC_DRAM,
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#endif
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