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Merge "intel: Refactor common platform code [5/5]" into integration

This commit is contained in:
Mark Dykes 2019-12-04 19:03:52 +00:00 committed by TrustedFirmware Code Review
parent b33772eb9c 1520b5d688
commit b3257a3d39
9 changed files with 54 additions and 83 deletions
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2
plat/intel/soc/agilex/bl2_plat_setup.c
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@ -14,14 +14,12 @@
#include <drivers/synopsys/dw_mmc.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <platform_def.h>
#include "agilex_clock_manager.h"
#include "agilex_memory_controller.h"
#include "agilex_pinmux.h"
#include "agilex_reset_manager.h"
#include "agilex_system_manager.h"
#include "ccu/ncore_ccu.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"

5
plat/intel/soc/agilex/bl31_plat_setup.c
View File

@ -12,7 +12,6 @@
#include <drivers/arm/gicv2.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <platform_def.h>
static entry_point_info_t bl32_image_ep_info;
@ -104,7 +103,7 @@ const mmap_region_t plat_agilex_mmap[] = {
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
{0},
{0}
};
/*******************************************************************************
@ -126,7 +125,7 @@ void bl31_plat_arch_setup(void)
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE),
#endif
{0},
{0}
};
setup_page_tables(bl_regions, plat_agilex_mmap);

34
plat/intel/soc/agilex/platform.mk
View File

@ -4,7 +4,7 @@
#
# SPDX-License-Identifier: BSD-3-Clause
#
#
PLAT_INCLUDES := \
-Iplat/intel/soc/agilex/include/ \
-Iplat/intel/soc/common/drivers/ \
@ -25,28 +25,26 @@ PLAT_BL_COMMON_SOURCES := \
BL2_SOURCES += \
common/desc_image_load.c \
drivers/partition/partition.c \
drivers/partition/gpt.c \
drivers/arm/pl061/pl061_gpio.c \
drivers/mmc/mmc.c \
drivers/synopsys/emmc/dw_mmc.c \
drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
drivers/io/io_storage.c \
drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/gpio/gpio.c \
drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
drivers/partition/partition.c \
drivers/partition/gpt.c \
drivers/synopsys/emmc/dw_mmc.c \
lib/cpus/aarch64/cortex_a53.S \
plat/intel/soc/agilex/bl2_plat_setup.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/agilex/soc/agilex_memory_controller.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_system_manager.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/agilex/soc/agilex_system_manager.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c \
@ -54,18 +52,14 @@ BL2_SOURCES += \
BL31_SOURCES += \
drivers/arm/cci/cci.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/agilex/bl31_plat_setup.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
plat/intel/soc/common/soc/socfpga_mailbox.c
plat/intel/soc/common/soc/socfpga_mailbox.c \
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1

1
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
View File

@ -10,7 +10,6 @@
#include <lib/mmio.h>
#include "ncore_ccu.h"
#include <platform_def.h>
uint32_t poll_active_bit(uint32_t dir);

1
plat/intel/soc/common/drivers/qspi/cadence_qspi.c
View File

@ -13,7 +13,6 @@
#include <drivers/console.h>
#include "cadence_qspi.h"
#include <platform_def.h>
#define LESS(a, b) (((a) < (b)) ? (a) : (b))
#define MORE(a, b) (((a) > (b)) ? (a) : (b))

1
plat/intel/soc/common/drivers/wdt/watchdog.c
View File

@ -6,7 +6,6 @@
#include <common/debug.h>
#include <lib/mmio.h>
#include <platform_def.h>
#include "watchdog.h"

23
plat/intel/soc/stratix10/bl2_plat_setup.c
View File

@ -1,36 +1,29 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <drivers/arm/gicv2.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/console.h>
#include <drivers/ti/uart/uart_16550.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <errno.h>
#include <drivers/io/io_storage.h>
#include <common/image_decompress.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/synopsys/dw_mmc.h>
#include <lib/mmio.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/xlat_tables/xlat_tables.h>
#include "s10_memory_controller.h"
#include "s10_reset_manager.h"
#include "s10_clock_manager.h"
#include "s10_pinmux.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
#include "s10_clock_manager.h"
#include "s10_memory_controller.h"
#include "s10_pinmux.h"
#include "s10_reset_manager.h"
#include "s10_system_manager.h"
#include "wdt/watchdog.h"

9
plat/intel/soc/stratix10/bl31_plat_setup.c
View File

@ -1,21 +1,16 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/console.h>
#include <drivers/delay_timer.h>
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gicv2.h>
#include <drivers/ti/uart/uart_16550.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/arm/gicv2.h>
#include <lib/xlat_tables/xlat_tables.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>

61
plat/intel/soc/stratix10/platform.mk
View File

@ -1,5 +1,6 @@
#
# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -10,60 +11,54 @@ PLAT_INCLUDES := \
-Iplat/intel/soc/common/include/
PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
plat/common/plat_gicv2.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S
BL2_SOURCES += \
drivers/partition/partition.c \
drivers/partition/gpt.c \
drivers/arm/pl061/pl061_gpio.c \
common/desc_image_load.c \
drivers/mmc/mmc.c \
drivers/synopsys/emmc/dw_mmc.c \
drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
drivers/io/io_storage.c \
drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/gpio/gpio.c \
drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
plat/intel/soc/stratix10/bl2_plat_setup.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/stratix10/soc/s10_clock_manager.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
plat/intel/soc/common/socfpga_delay_timer.c \
drivers/partition/partition.c \
drivers/partition/gpt.c \
drivers/synopsys/emmc/dw_mmc.c \
lib/cpus/aarch64/cortex_a53.S \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/stratix10/bl2_plat_setup.c \
plat/intel/soc/stratix10/soc/s10_clock_manager.c \
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c \
plat/intel/soc/stratix10/soc/s10_system_manager.c \
common/desc_image_load.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c
BL31_SOURCES += drivers/arm/cci/cci.c \
BL31_SOURCES += \
drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/stratix10/bl31_plat_setup.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c\
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/stratix10/soc/s10_clock_manager.c\
plat/intel/soc/common/soc/socfpga_mailbox.c
plat/common/plat_psci_common.c \
plat/intel/soc/stratix10/bl31_plat_setup.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1