rcar_gen3: drivers: pfc: V3M: Switch to BIT() macro
Utilise existing BIT() macro. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I0f6c1cadf51cfe49322ec5408e6661287747e0ae
This commit is contained in:
Marek Vasut
parent
4891ca8b17
commit
b4732f0643
|
|
@ -13,116 +13,116 @@
|
|||
#include "../pfc_regs.h"
|
||||
|
||||
/* Pin functon bit */
|
||||
#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define GPSR0_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define GPSR0_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define GPSR0_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define GPSR0_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define GPSR0_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define GPSR0_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define GPSR0_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define GPSR0_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define GPSR0_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define GPSR0_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define GPSR0_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define GPSR0_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define GPSR0_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define GPSR0_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define GPSR0_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define GPSR0_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define GPSR0_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define GPSR0_DU_DR2 ((uint32_t)1U << 0U)
|
||||
#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
|
||||
#define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)
|
||||
#define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)
|
||||
#define GPSR0_DU_DOTCLKOUT BIT(18)
|
||||
#define GPSR0_DU_DB7 BIT(17)
|
||||
#define GPSR0_DU_DB6 BIT(16)
|
||||
#define GPSR0_DU_DB5 BIT(15)
|
||||
#define GPSR0_DU_DB4 BIT(14)
|
||||
#define GPSR0_DU_DB3 BIT(13)
|
||||
#define GPSR0_DU_DB2 BIT(12)
|
||||
#define GPSR0_DU_DG7 BIT(11)
|
||||
#define GPSR0_DU_DG6 BIT(10)
|
||||
#define GPSR0_DU_DG5 BIT(9)
|
||||
#define GPSR0_DU_DG4 BIT(8)
|
||||
#define GPSR0_DU_DG3 BIT(7)
|
||||
#define GPSR0_DU_DG2 BIT(6)
|
||||
#define GPSR0_DU_DR7 BIT(5)
|
||||
#define GPSR0_DU_DR6 BIT(4)
|
||||
#define GPSR0_DU_DR5 BIT(3)
|
||||
#define GPSR0_DU_DR4 BIT(2)
|
||||
#define GPSR0_DU_DR3 BIT(1)
|
||||
#define GPSR0_DU_DR2 BIT(0)
|
||||
|
||||
#define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U)
|
||||
#define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U)
|
||||
#define GPSR1_CANFD_CLK ((uint32_t)1U << 25U)
|
||||
#define GPSR1_CANFD1_RX ((uint32_t)1U << 24U)
|
||||
#define GPSR1_CANFD1_TX ((uint32_t)1U << 23U)
|
||||
#define GPSR1_CANFD0_RX ((uint32_t)1U << 22U)
|
||||
#define GPSR1_CANFD0_TX ((uint32_t)1U << 21U)
|
||||
#define GPSR1_AVB0_AVTP_CAPTURE ((uint32_t)1U << 20U)
|
||||
#define GPSR1_AVB0_AVTP_MATCH ((uint32_t)1U << 19U)
|
||||
#define GPSR1_AVB0_LINK ((uint32_t)1U << 18U)
|
||||
#define GPSR1_AVB0_PHY_INT ((uint32_t)1U << 17U)
|
||||
#define GPSR1_AVB0_MAGIC ((uint32_t)1U << 16U)
|
||||
#define GPSR1_AVB0_MDC ((uint32_t)1U << 15U)
|
||||
#define GPSR1_AVB0_MDIO ((uint32_t)1U << 14U)
|
||||
#define GPSR1_AVB0_TXCREFCLK ((uint32_t)1U << 13U)
|
||||
#define GPSR1_AVB0_TD3 ((uint32_t)1U << 12U)
|
||||
#define GPSR1_AVB0_TD2 ((uint32_t)1U << 11U)
|
||||
#define GPSR1_AVB0_TD1 ((uint32_t)1U << 10U)
|
||||
#define GPSR1_AVB0_TD0 ((uint32_t)1U << 9U)
|
||||
#define GPSR1_AVB0_TXC ((uint32_t)1U << 8U)
|
||||
#define GPSR1_AVB0_TX_CTL ((uint32_t)1U << 7U)
|
||||
#define GPSR1_AVB0_RD3 ((uint32_t)1U << 6U)
|
||||
#define GPSR1_AVB0_RD2 ((uint32_t)1U << 5U)
|
||||
#define GPSR1_AVB0_RD1 ((uint32_t)1U << 4U)
|
||||
#define GPSR1_AVB0_RD0 ((uint32_t)1U << 3U)
|
||||
#define GPSR1_AVB0_RXC ((uint32_t)1U << 2U)
|
||||
#define GPSR1_AVB0_RX_CTL ((uint32_t)1U << 1U)
|
||||
#define GPSR1_IRQ0 ((uint32_t)1U << 0U)
|
||||
#define GPSR1_DIGRF_CLKOUT BIT(27)
|
||||
#define GPSR1_DIGRF_CLKIN BIT(26)
|
||||
#define GPSR1_CANFD_CLK BIT(25)
|
||||
#define GPSR1_CANFD1_RX BIT(24)
|
||||
#define GPSR1_CANFD1_TX BIT(23)
|
||||
#define GPSR1_CANFD0_RX BIT(22)
|
||||
#define GPSR1_CANFD0_TX BIT(21)
|
||||
#define GPSR1_AVB0_AVTP_CAPTURE BIT(20)
|
||||
#define GPSR1_AVB0_AVTP_MATCH BIT(19)
|
||||
#define GPSR1_AVB0_LINK BIT(18)
|
||||
#define GPSR1_AVB0_PHY_INT BIT(17)
|
||||
#define GPSR1_AVB0_MAGIC BIT(16)
|
||||
#define GPSR1_AVB0_MDC BIT(15)
|
||||
#define GPSR1_AVB0_MDIO BIT(14)
|
||||
#define GPSR1_AVB0_TXCREFCLK BIT(13)
|
||||
#define GPSR1_AVB0_TD3 BIT(12)
|
||||
#define GPSR1_AVB0_TD2 BIT(11)
|
||||
#define GPSR1_AVB0_TD1 BIT(10)
|
||||
#define GPSR1_AVB0_TD0 BIT(9)
|
||||
#define GPSR1_AVB0_TXC BIT(8)
|
||||
#define GPSR1_AVB0_TX_CTL BIT(7)
|
||||
#define GPSR1_AVB0_RD3 BIT(6)
|
||||
#define GPSR1_AVB0_RD2 BIT(5)
|
||||
#define GPSR1_AVB0_RD1 BIT(4)
|
||||
#define GPSR1_AVB0_RD0 BIT(3)
|
||||
#define GPSR1_AVB0_RXC BIT(2)
|
||||
#define GPSR1_AVB0_RX_CTL BIT(1)
|
||||
#define GPSR1_IRQ0 BIT(0)
|
||||
|
||||
#define GPSR2_VI0_FIELD ((uint32_t)1U << 16U)
|
||||
#define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U)
|
||||
#define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U)
|
||||
#define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U)
|
||||
#define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U)
|
||||
#define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U)
|
||||
#define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U)
|
||||
#define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U)
|
||||
#define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U)
|
||||
#define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U)
|
||||
#define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U)
|
||||
#define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U)
|
||||
#define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U)
|
||||
#define GPSR2_VI0_VSYNC_N ((uint32_t)1U << 3U)
|
||||
#define GPSR2_VI0_HSYNC_N ((uint32_t)1U << 2U)
|
||||
#define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U)
|
||||
#define GPSR2_VI0_CLK ((uint32_t)1U << 0U)
|
||||
#define GPSR2_VI0_FIELD BIT(16)
|
||||
#define GPSR2_VI0_DATA11 BIT(15)
|
||||
#define GPSR2_VI0_DATA10 BIT(14)
|
||||
#define GPSR2_VI0_DATA9 BIT(13)
|
||||
#define GPSR2_VI0_DATA8 BIT(12)
|
||||
#define GPSR2_VI0_DATA7 BIT(11)
|
||||
#define GPSR2_VI0_DATA6 BIT(10)
|
||||
#define GPSR2_VI0_DATA5 BIT(9)
|
||||
#define GPSR2_VI0_DATA4 BIT(8)
|
||||
#define GPSR2_VI0_DATA3 BIT(7)
|
||||
#define GPSR2_VI0_DATA2 BIT(6)
|
||||
#define GPSR2_VI0_DATA1 BIT(5)
|
||||
#define GPSR2_VI0_DATA0 BIT(4)
|
||||
#define GPSR2_VI0_VSYNC_N BIT(3)
|
||||
#define GPSR2_VI0_HSYNC_N BIT(2)
|
||||
#define GPSR2_VI0_CLKENB BIT(1)
|
||||
#define GPSR2_VI0_CLK BIT(0)
|
||||
|
||||
#define GPSR3_VI1_FIELD ((uint32_t)1U << 16U)
|
||||
#define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U)
|
||||
#define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U)
|
||||
#define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U)
|
||||
#define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U)
|
||||
#define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U)
|
||||
#define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U)
|
||||
#define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U)
|
||||
#define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U)
|
||||
#define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U)
|
||||
#define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U)
|
||||
#define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U)
|
||||
#define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U)
|
||||
#define GPSR3_VI1_VSYNC_N ((uint32_t)1U << 3U)
|
||||
#define GPSR3_VI1_HSYNC_N ((uint32_t)1U << 2U)
|
||||
#define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U)
|
||||
#define GPSR3_VI1_CLK ((uint32_t)1U << 0U)
|
||||
#define GPSR3_VI1_FIELD BIT(16)
|
||||
#define GPSR3_VI1_DATA11 BIT(15)
|
||||
#define GPSR3_VI1_DATA10 BIT(14)
|
||||
#define GPSR3_VI1_DATA9 BIT(13)
|
||||
#define GPSR3_VI1_DATA8 BIT(12)
|
||||
#define GPSR3_VI1_DATA7 BIT(11)
|
||||
#define GPSR3_VI1_DATA6 BIT(10)
|
||||
#define GPSR3_VI1_DATA5 BIT(9)
|
||||
#define GPSR3_VI1_DATA4 BIT(8)
|
||||
#define GPSR3_VI1_DATA3 BIT(7)
|
||||
#define GPSR3_VI1_DATA2 BIT(6)
|
||||
#define GPSR3_VI1_DATA1 BIT(5)
|
||||
#define GPSR3_VI1_DATA0 BIT(4)
|
||||
#define GPSR3_VI1_VSYNC_N BIT(3)
|
||||
#define GPSR3_VI1_HSYNC_N BIT(2)
|
||||
#define GPSR3_VI1_CLKENB BIT(1)
|
||||
#define GPSR3_VI1_CLK BIT(0)
|
||||
|
||||
#define GPSR4_SDA2 ((uint32_t)1U << 5U)
|
||||
#define GPSR4_SCL2 ((uint32_t)1U << 4U)
|
||||
#define GPSR4_SDA1 ((uint32_t)1U << 3U)
|
||||
#define GPSR4_SCL1 ((uint32_t)1U << 2U)
|
||||
#define GPSR4_SDA0 ((uint32_t)1U << 1U)
|
||||
#define GPSR4_SCL0 ((uint32_t)1U << 0U)
|
||||
#define GPSR4_SDA2 BIT(5)
|
||||
#define GPSR4_SCL2 BIT(4)
|
||||
#define GPSR4_SDA1 BIT(3)
|
||||
#define GPSR4_SCL1 BIT(2)
|
||||
#define GPSR4_SDA0 BIT(1)
|
||||
#define GPSR4_SCL0 BIT(0)
|
||||
|
||||
#define GPSR5_RPC_INT_N ((uint32_t)1U << 14U)
|
||||
#define GPSR5_RPC_WP_N ((uint32_t)1U << 13U)
|
||||
#define GPSR5_RPC_RESET_N ((uint32_t)1U << 12U)
|
||||
#define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U)
|
||||
#define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U)
|
||||
#define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U)
|
||||
#define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
|
||||
#define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
|
||||
#define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U)
|
||||
#define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U)
|
||||
#define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U)
|
||||
#define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U)
|
||||
#define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
|
||||
#define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
|
||||
#define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U)
|
||||
#define GPSR5_RPC_INT_N BIT(14)
|
||||
#define GPSR5_RPC_WP_N BIT(13)
|
||||
#define GPSR5_RPC_RESET_N BIT(12)
|
||||
#define GPSR5_QSPI1_SSL BIT(11)
|
||||
#define GPSR5_QSPI1_IO3 BIT(10)
|
||||
#define GPSR5_QSPI1_IO2 BIT(9)
|
||||
#define GPSR5_QSPI1_MISO_IO1 BIT(8)
|
||||
#define GPSR5_QSPI1_MOSI_IO0 BIT(7)
|
||||
#define GPSR5_QSPI1_SPCLK BIT(6)
|
||||
#define GPSR5_QSPI0_SSL BIT(5)
|
||||
#define GPSR5_QSPI0_IO3 BIT(4)
|
||||
#define GPSR5_QSPI0_IO2 BIT(3)
|
||||
#define GPSR5_QSPI0_MISO_IO1 BIT(2)
|
||||
#define GPSR5_QSPI0_MOSI_IO0 BIT(1)
|
||||
#define GPSR5_QSPI0_SPCLK BIT(0)
|
||||
|
||||
#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
|
||||
#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
|
||||
|
|
@ -133,314 +133,314 @@
|
|||
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
|
||||
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
|
||||
|
||||
#define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U)
|
||||
#define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U)
|
||||
#define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U)
|
||||
#define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U)
|
||||
#define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U)
|
||||
#define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U)
|
||||
#define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U)
|
||||
#define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U)
|
||||
#define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U)
|
||||
#define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U)
|
||||
#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U)
|
||||
#define IOCTRL30_POC_VI0_DATA5 BIT(31)
|
||||
#define IOCTRL30_POC_VI0_DATA4 BIT(30)
|
||||
#define IOCTRL30_POC_VI0_DATA3 BIT(29)
|
||||
#define IOCTRL30_POC_VI0_DATA2 BIT(28)
|
||||
#define IOCTRL30_POC_VI0_DATA1 BIT(27)
|
||||
#define IOCTRL30_POC_VI0_DATA0 BIT(26)
|
||||
#define IOCTRL30_POC_VI0_VSYNC_N BIT(25)
|
||||
#define IOCTRL30_POC_VI0_HSYNC_N BIT(24)
|
||||
#define IOCTRL30_POC_VI0_CLKENB BIT(23)
|
||||
#define IOCTRL30_POC_VI0_CLK BIT(22)
|
||||
#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
|
||||
#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC BIT(20)
|
||||
#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC BIT(19)
|
||||
#define IOCTRL30_POC_DU_DOTCLKOUT BIT(18)
|
||||
#define IOCTRL30_POC_DU_DB7 BIT(17)
|
||||
#define IOCTRL30_POC_DU_DB6 BIT(16)
|
||||
#define IOCTRL30_POC_DU_DB5 BIT(15)
|
||||
#define IOCTRL30_POC_DU_DB4 BIT(14)
|
||||
#define IOCTRL30_POC_DU_DB3 BIT(13)
|
||||
#define IOCTRL30_POC_DU_DB2 BIT(12)
|
||||
#define IOCTRL30_POC_DU_DG7 BIT(11)
|
||||
#define IOCTRL30_POC_DU_DG6 BIT(10)
|
||||
#define IOCTRL30_POC_DU_DG5 BIT(9)
|
||||
#define IOCTRL30_POC_DU_DG4 BIT(8)
|
||||
#define IOCTRL30_POC_DU_DG3 BIT(7)
|
||||
#define IOCTRL30_POC_DU_DG2 BIT(6)
|
||||
#define IOCTRL30_POC_DU_DR7 BIT(5)
|
||||
#define IOCTRL30_POC_DU_DR6 BIT(4)
|
||||
#define IOCTRL30_POC_DU_DR5 BIT(3)
|
||||
#define IOCTRL30_POC_DU_DR4 BIT(2)
|
||||
#define IOCTRL30_POC_DU_DR3 BIT(1)
|
||||
#define IOCTRL30_POC_DU_DR2 BIT(0)
|
||||
|
||||
#define IOCTRL31_POC_DUMMY_31 ((uint32_t)1U << 31U)
|
||||
#define IOCTRL31_POC_DUMMY_30 ((uint32_t)1U << 30U)
|
||||
#define IOCTRL31_POC_DUMMY_29 ((uint32_t)1U << 29U)
|
||||
#define IOCTRL31_POC_DUMMY_28 ((uint32_t)1U << 28U)
|
||||
#define IOCTRL31_POC_DUMMY_27 ((uint32_t)1U << 27U)
|
||||
#define IOCTRL31_POC_DUMMY_26 ((uint32_t)1U << 26U)
|
||||
#define IOCTRL31_POC_DUMMY_25 ((uint32_t)1U << 25U)
|
||||
#define IOCTRL31_POC_DUMMY_24 ((uint32_t)1U << 24U)
|
||||
#define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U)
|
||||
#define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U)
|
||||
#define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U)
|
||||
#define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U)
|
||||
#define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U)
|
||||
#define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U)
|
||||
#define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U)
|
||||
#define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U)
|
||||
#define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U)
|
||||
#define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U)
|
||||
#define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U)
|
||||
#define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U)
|
||||
#define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U)
|
||||
#define IOCTRL31_POC_VI1_VSYNC_N ((uint32_t)1U << 10U)
|
||||
#define IOCTRL31_POC_VI1_HSYNC_N ((uint32_t)1U << 9U)
|
||||
#define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U)
|
||||
#define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U)
|
||||
#define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U)
|
||||
#define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U)
|
||||
#define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U)
|
||||
#define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U)
|
||||
#define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U)
|
||||
#define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U)
|
||||
#define IOCTRL32_POC2_VREF ((uint32_t)1U << 0U)
|
||||
#define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U)
|
||||
#define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U)
|
||||
#define IOCTRL31_POC_DUMMY_31 BIT(31)
|
||||
#define IOCTRL31_POC_DUMMY_30 BIT(30)
|
||||
#define IOCTRL31_POC_DUMMY_29 BIT(29)
|
||||
#define IOCTRL31_POC_DUMMY_28 BIT(28)
|
||||
#define IOCTRL31_POC_DUMMY_27 BIT(27)
|
||||
#define IOCTRL31_POC_DUMMY_26 BIT(26)
|
||||
#define IOCTRL31_POC_DUMMY_25 BIT(25)
|
||||
#define IOCTRL31_POC_DUMMY_24 BIT(24)
|
||||
#define IOCTRL31_POC_VI1_FIELD BIT(23)
|
||||
#define IOCTRL31_POC_VI1_DATA11 BIT(22)
|
||||
#define IOCTRL31_POC_VI1_DATA10 BIT(21)
|
||||
#define IOCTRL31_POC_VI1_DATA9 BIT(20)
|
||||
#define IOCTRL31_POC_VI1_DATA8 BIT(19)
|
||||
#define IOCTRL31_POC_VI1_DATA7 BIT(18)
|
||||
#define IOCTRL31_POC_VI1_DATA6 BIT(17)
|
||||
#define IOCTRL31_POC_VI1_DATA5 BIT(16)
|
||||
#define IOCTRL31_POC_VI1_DATA4 BIT(15)
|
||||
#define IOCTRL31_POC_VI1_DATA3 BIT(14)
|
||||
#define IOCTRL31_POC_VI1_DATA2 BIT(13)
|
||||
#define IOCTRL31_POC_VI1_DATA1 BIT(12)
|
||||
#define IOCTRL31_POC_VI1_DATA0 BIT(11)
|
||||
#define IOCTRL31_POC_VI1_VSYNC_N BIT(10)
|
||||
#define IOCTRL31_POC_VI1_HSYNC_N BIT(9)
|
||||
#define IOCTRL31_POC_VI1_CLKENB BIT(8)
|
||||
#define IOCTRL31_POC_VI1_CLK BIT(7)
|
||||
#define IOCTRL31_POC_VI0_FIELD BIT(6)
|
||||
#define IOCTRL31_POC_VI0_DATA11 BIT(5)
|
||||
#define IOCTRL31_POC_VI0_DATA10 BIT(4)
|
||||
#define IOCTRL31_POC_VI0_DATA9 BIT(3)
|
||||
#define IOCTRL31_POC_VI0_DATA8 BIT(2)
|
||||
#define IOCTRL31_POC_VI0_DATA7 BIT(1)
|
||||
#define IOCTRL31_POC_VI0_DATA6 BIT(0)
|
||||
#define IOCTRL32_POC2_VREF BIT(0)
|
||||
#define IOCTRL40_SD0TDSEL1 BIT(1)
|
||||
#define IOCTRL40_SD0TDSEL0 BIT(0)
|
||||
|
||||
#define PUEN0_PUEN_VI0_CLK ((uint32_t)1U << 31U)
|
||||
#define PUEN0_PUEN_TDI ((uint32_t)1U << 30U)
|
||||
#define PUEN0_PUEN_TMS ((uint32_t)1U << 29U)
|
||||
#define PUEN0_PUEN_TCK ((uint32_t)1U << 28U)
|
||||
#define PUEN0_PUEN_TRST_N ((uint32_t)1U << 27U)
|
||||
#define PUEN0_PUEN_IRQ0 ((uint32_t)1U << 26U)
|
||||
#define PUEN0_PUEN_FSCLKST_N ((uint32_t)1U << 25U)
|
||||
#define PUEN0_PUEN_EXTALR ((uint32_t)1U << 24U)
|
||||
#define PUEN0_PUEN_PRESETOUT_N ((uint32_t)1U << 23U)
|
||||
#define PUEN0_PUEN_DU_DOTCLKIN ((uint32_t)1U << 22U)
|
||||
#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define PUEN0_PUEN_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define PUEN0_PUEN_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define PUEN0_PUEN_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define PUEN0_PUEN_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define PUEN0_PUEN_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define PUEN0_PUEN_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define PUEN0_PUEN_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define PUEN0_PUEN_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define PUEN0_PUEN_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define PUEN0_PUEN_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define PUEN0_PUEN_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define PUEN0_PUEN_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define PUEN0_PUEN_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define PUEN0_PUEN_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define PUEN0_PUEN_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define PUEN0_PUEN_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define PUEN0_PUEN_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define PUEN0_PUEN_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define PUEN0_PUEN_DU_DR2 ((uint32_t)1U << 0U)
|
||||
#define PUEN0_PUEN_VI0_CLK BIT(31)
|
||||
#define PUEN0_PUEN_TDI BIT(30)
|
||||
#define PUEN0_PUEN_TMS BIT(29)
|
||||
#define PUEN0_PUEN_TCK BIT(28)
|
||||
#define PUEN0_PUEN_TRST_N BIT(27)
|
||||
#define PUEN0_PUEN_IRQ0 BIT(26)
|
||||
#define PUEN0_PUEN_FSCLKST_N BIT(25)
|
||||
#define PUEN0_PUEN_EXTALR BIT(24)
|
||||
#define PUEN0_PUEN_PRESETOUT_N BIT(23)
|
||||
#define PUEN0_PUEN_DU_DOTCLKIN BIT(22)
|
||||
#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
|
||||
#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC BIT(20)
|
||||
#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC BIT(19)
|
||||
#define PUEN0_PUEN_DU_DOTCLKOUT BIT(18)
|
||||
#define PUEN0_PUEN_DU_DB7 BIT(17)
|
||||
#define PUEN0_PUEN_DU_DB6 BIT(16)
|
||||
#define PUEN0_PUEN_DU_DB5 BIT(15)
|
||||
#define PUEN0_PUEN_DU_DB4 BIT(14)
|
||||
#define PUEN0_PUEN_DU_DB3 BIT(13)
|
||||
#define PUEN0_PUEN_DU_DB2 BIT(12)
|
||||
#define PUEN0_PUEN_DU_DG7 BIT(11)
|
||||
#define PUEN0_PUEN_DU_DG6 BIT(10)
|
||||
#define PUEN0_PUEN_DU_DG5 BIT(9)
|
||||
#define PUEN0_PUEN_DU_DG4 BIT(8)
|
||||
#define PUEN0_PUEN_DU_DG3 BIT(7)
|
||||
#define PUEN0_PUEN_DU_DG2 BIT(6)
|
||||
#define PUEN0_PUEN_DU_DR7 BIT(5)
|
||||
#define PUEN0_PUEN_DU_DR6 BIT(4)
|
||||
#define PUEN0_PUEN_DU_DR5 BIT(3)
|
||||
#define PUEN0_PUEN_DU_DR4 BIT(2)
|
||||
#define PUEN0_PUEN_DU_DR3 BIT(1)
|
||||
#define PUEN0_PUEN_DU_DR2 BIT(0)
|
||||
|
||||
#define PUEN1_PUEN_VI1_DATA11 ((uint32_t)1U << 31U)
|
||||
#define PUEN1_PUEN_VI1_DATA10 ((uint32_t)1U << 30U)
|
||||
#define PUEN1_PUEN_VI1_DATA9 ((uint32_t)1U << 29U)
|
||||
#define PUEN1_PUEN_VI1_DATA8 ((uint32_t)1U << 28U)
|
||||
#define PUEN1_PUEN_VI1_DATA7 ((uint32_t)1U << 27U)
|
||||
#define PUEN1_PUEN_VI1_DATA6 ((uint32_t)1U << 26U)
|
||||
#define PUEN1_PUEN_VI1_DATA5 ((uint32_t)1U << 25U)
|
||||
#define PUEN1_PUEN_VI1_DATA4 ((uint32_t)1U << 24U)
|
||||
#define PUEN1_PUEN_VI1_DATA3 ((uint32_t)1U << 23U)
|
||||
#define PUEN1_PUEN_VI1_DATA2 ((uint32_t)1U << 22U)
|
||||
#define PUEN1_PUEN_VI1_DATA1 ((uint32_t)1U << 21U)
|
||||
#define PUEN1_PUEN_VI1_DATA0 ((uint32_t)1U << 20U)
|
||||
#define PUEN1_PUEN_VI1_VSYNC_N ((uint32_t)1U << 19U)
|
||||
#define PUEN1_PUEN_VI1_HSYNC_N ((uint32_t)1U << 18U)
|
||||
#define PUEN1_PUEN_VI1_CLKENB ((uint32_t)1U << 17U)
|
||||
#define PUEN1_PUEN_VI1_CLK ((uint32_t)1U << 16U)
|
||||
#define PUEN1_PUEN_VI0_FIELD ((uint32_t)1U << 15U)
|
||||
#define PUEN1_PUEN_VI0_DATA11 ((uint32_t)1U << 14U)
|
||||
#define PUEN1_PUEN_VI0_DATA10 ((uint32_t)1U << 13U)
|
||||
#define PUEN1_PUEN_VI0_DATA9 ((uint32_t)1U << 12U)
|
||||
#define PUEN1_PUEN_VI0_DATA8 ((uint32_t)1U << 11U)
|
||||
#define PUEN1_PUEN_VI0_DATA7 ((uint32_t)1U << 10U)
|
||||
#define PUEN1_PUEN_VI0_DATA6 ((uint32_t)1U << 9U)
|
||||
#define PUEN1_PUEN_VI0_DATA5 ((uint32_t)1U << 8U)
|
||||
#define PUEN1_PUEN_VI0_DATA4 ((uint32_t)1U << 7U)
|
||||
#define PUEN1_PUEN_VI0_DATA3 ((uint32_t)1U << 6U)
|
||||
#define PUEN1_PUEN_VI0_DATA2 ((uint32_t)1U << 5U)
|
||||
#define PUEN1_PUEN_VI0_DATA1 ((uint32_t)1U << 4U)
|
||||
#define PUEN1_PUEN_VI0_DATA0 ((uint32_t)1U << 3U)
|
||||
#define PUEN1_PUEN_VI0_VSYNC_N ((uint32_t)1U << 2U)
|
||||
#define PUEN1_PUEN_VI0_HSYNC_N ((uint32_t)1U << 1U)
|
||||
#define PUEN1_PUEN_VI0_CLKENB ((uint32_t)1U << 0U)
|
||||
#define PUEN1_PUEN_VI1_DATA11 BIT(31)
|
||||
#define PUEN1_PUEN_VI1_DATA10 BIT(30)
|
||||
#define PUEN1_PUEN_VI1_DATA9 BIT(29)
|
||||
#define PUEN1_PUEN_VI1_DATA8 BIT(28)
|
||||
#define PUEN1_PUEN_VI1_DATA7 BIT(27)
|
||||
#define PUEN1_PUEN_VI1_DATA6 BIT(26)
|
||||
#define PUEN1_PUEN_VI1_DATA5 BIT(25)
|
||||
#define PUEN1_PUEN_VI1_DATA4 BIT(24)
|
||||
#define PUEN1_PUEN_VI1_DATA3 BIT(23)
|
||||
#define PUEN1_PUEN_VI1_DATA2 BIT(22)
|
||||
#define PUEN1_PUEN_VI1_DATA1 BIT(21)
|
||||
#define PUEN1_PUEN_VI1_DATA0 BIT(20)
|
||||
#define PUEN1_PUEN_VI1_VSYNC_N BIT(19)
|
||||
#define PUEN1_PUEN_VI1_HSYNC_N BIT(18)
|
||||
#define PUEN1_PUEN_VI1_CLKENB BIT(17)
|
||||
#define PUEN1_PUEN_VI1_CLK BIT(16)
|
||||
#define PUEN1_PUEN_VI0_FIELD BIT(15)
|
||||
#define PUEN1_PUEN_VI0_DATA11 BIT(14)
|
||||
#define PUEN1_PUEN_VI0_DATA10 BIT(13)
|
||||
#define PUEN1_PUEN_VI0_DATA9 BIT(12)
|
||||
#define PUEN1_PUEN_VI0_DATA8 BIT(11)
|
||||
#define PUEN1_PUEN_VI0_DATA7 BIT(10)
|
||||
#define PUEN1_PUEN_VI0_DATA6 BIT(9)
|
||||
#define PUEN1_PUEN_VI0_DATA5 BIT(8)
|
||||
#define PUEN1_PUEN_VI0_DATA4 BIT(7)
|
||||
#define PUEN1_PUEN_VI0_DATA3 BIT(6)
|
||||
#define PUEN1_PUEN_VI0_DATA2 BIT(5)
|
||||
#define PUEN1_PUEN_VI0_DATA1 BIT(4)
|
||||
#define PUEN1_PUEN_VI0_DATA0 BIT(3)
|
||||
#define PUEN1_PUEN_VI0_VSYNC_N BIT(2)
|
||||
#define PUEN1_PUEN_VI0_HSYNC_N BIT(1)
|
||||
#define PUEN1_PUEN_VI0_CLKENB BIT(0)
|
||||
|
||||
#define PUEN2_PUEN_CANFD_CLK ((uint32_t)1U << 31U)
|
||||
#define PUEN2_PUEN_CANFD1_RX ((uint32_t)1U << 30U)
|
||||
#define PUEN2_PUEN_CANFD1_TX ((uint32_t)1U << 29U)
|
||||
#define PUEN2_PUEN_CANFD0_RX ((uint32_t)1U << 28U)
|
||||
#define PUEN2_PUEN_CANFD0_TX ((uint32_t)1U << 27U)
|
||||
#define PUEN2_PUEN_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U)
|
||||
#define PUEN2_PUEN_AVB0_AVTP_MATCH ((uint32_t)1U << 25U)
|
||||
#define PUEN2_PUEN_AVB0_LINK ((uint32_t)1U << 24U)
|
||||
#define PUEN2_PUEN_AVB0_PHY_INT ((uint32_t)1U << 23U)
|
||||
#define PUEN2_PUEN_AVB0_MAGIC ((uint32_t)1U << 22U)
|
||||
#define PUEN2_PUEN_AVB0_MDC ((uint32_t)1U << 21U)
|
||||
#define PUEN2_PUEN_AVB0_MDIO ((uint32_t)1U << 20U)
|
||||
#define PUEN2_PUEN_AVB0_TXCREFCLK ((uint32_t)1U << 19U)
|
||||
#define PUEN2_PUEN_AVB0_TD3 ((uint32_t)1U << 18U)
|
||||
#define PUEN2_PUEN_AVB0_TD2 ((uint32_t)1U << 17U)
|
||||
#define PUEN2_PUEN_AVB0_TD1 ((uint32_t)1U << 16U)
|
||||
#define PUEN2_PUEN_AVB0_TD0 ((uint32_t)1U << 15U)
|
||||
#define PUEN2_PUEN_AVB0_TXC ((uint32_t)1U << 14U)
|
||||
#define PUEN2_PUEN_AVB0_TX_CTL ((uint32_t)1U << 13U)
|
||||
#define PUEN2_PUEN_AVB0_RD3 ((uint32_t)1U << 12U)
|
||||
#define PUEN2_PUEN_AVB0_RD2 ((uint32_t)1U << 11U)
|
||||
#define PUEN2_PUEN_AVB0_RD1 ((uint32_t)1U << 10U)
|
||||
#define PUEN2_PUEN_AVB0_RD0 ((uint32_t)1U << 9U)
|
||||
#define PUEN2_PUEN_AVB0_RXC ((uint32_t)1U << 8U)
|
||||
#define PUEN2_PUEN_AVB0_RX_CTL ((uint32_t)1U << 7U)
|
||||
#define PUEN2_PUEN_SDA2 ((uint32_t)1U << 6U)
|
||||
#define PUEN2_PUEN_SCL2 ((uint32_t)1U << 5U)
|
||||
#define PUEN2_PUEN_SDA1 ((uint32_t)1U << 4U)
|
||||
#define PUEN2_PUEN_SCL1 ((uint32_t)1U << 3U)
|
||||
#define PUEN2_PUEN_SDA0 ((uint32_t)1U << 2U)
|
||||
#define PUEN2_PUEN_SCL0 ((uint32_t)1U << 1U)
|
||||
#define PUEN2_PUEN_VI1_FIELD ((uint32_t)1U << 0U)
|
||||
#define PUEN2_PUEN_CANFD_CLK BIT(31)
|
||||
#define PUEN2_PUEN_CANFD1_RX BIT(30)
|
||||
#define PUEN2_PUEN_CANFD1_TX BIT(29)
|
||||
#define PUEN2_PUEN_CANFD0_RX BIT(28)
|
||||
#define PUEN2_PUEN_CANFD0_TX BIT(27)
|
||||
#define PUEN2_PUEN_AVB0_AVTP_CAPTURE BIT(26)
|
||||
#define PUEN2_PUEN_AVB0_AVTP_MATCH BIT(25)
|
||||
#define PUEN2_PUEN_AVB0_LINK BIT(24)
|
||||
#define PUEN2_PUEN_AVB0_PHY_INT BIT(23)
|
||||
#define PUEN2_PUEN_AVB0_MAGIC BIT(22)
|
||||
#define PUEN2_PUEN_AVB0_MDC BIT(21)
|
||||
#define PUEN2_PUEN_AVB0_MDIO BIT(20)
|
||||
#define PUEN2_PUEN_AVB0_TXCREFCLK BIT(19)
|
||||
#define PUEN2_PUEN_AVB0_TD3 BIT(18)
|
||||
#define PUEN2_PUEN_AVB0_TD2 BIT(17)
|
||||
#define PUEN2_PUEN_AVB0_TD1 BIT(16)
|
||||
#define PUEN2_PUEN_AVB0_TD0 BIT(15)
|
||||
#define PUEN2_PUEN_AVB0_TXC BIT(14)
|
||||
#define PUEN2_PUEN_AVB0_TX_CTL BIT(13)
|
||||
#define PUEN2_PUEN_AVB0_RD3 BIT(12)
|
||||
#define PUEN2_PUEN_AVB0_RD2 BIT(11)
|
||||
#define PUEN2_PUEN_AVB0_RD1 BIT(10)
|
||||
#define PUEN2_PUEN_AVB0_RD0 BIT(9)
|
||||
#define PUEN2_PUEN_AVB0_RXC BIT(8)
|
||||
#define PUEN2_PUEN_AVB0_RX_CTL BIT(7)
|
||||
#define PUEN2_PUEN_SDA2 BIT(6)
|
||||
#define PUEN2_PUEN_SCL2 BIT(5)
|
||||
#define PUEN2_PUEN_SDA1 BIT(4)
|
||||
#define PUEN2_PUEN_SCL1 BIT(3)
|
||||
#define PUEN2_PUEN_SDA0 BIT(2)
|
||||
#define PUEN2_PUEN_SCL0 BIT(1)
|
||||
#define PUEN2_PUEN_VI1_FIELD BIT(0)
|
||||
|
||||
#define PUEN3_PUEN_DIGRF_CLKOUT ((uint32_t)1U << 16U)
|
||||
#define PUEN3_PUEN_DIGRF_CLKIN ((uint32_t)1U << 15U)
|
||||
#define PUEN3_PUEN_RPC_INT_N ((uint32_t)1U << 14U)
|
||||
#define PUEN3_PUEN_RPC_WP_N ((uint32_t)1U << 13U)
|
||||
#define PUEN3_PUEN_RPC_RESET_N ((uint32_t)1U << 12U)
|
||||
#define PUEN3_PUEN_QSPI1_SSL ((uint32_t)1U << 11U)
|
||||
#define PUEN3_PUEN_QSPI1_IO3 ((uint32_t)1U << 10U)
|
||||
#define PUEN3_PUEN_QSPI1_IO2 ((uint32_t)1U << 9U)
|
||||
#define PUEN3_PUEN_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
|
||||
#define PUEN3_PUEN_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
|
||||
#define PUEN3_PUEN_QSPI1_SPCLK ((uint32_t)1U << 6U)
|
||||
#define PUEN3_PUEN_QSPI0_SSL ((uint32_t)1U << 5U)
|
||||
#define PUEN3_PUEN_QSPI0_IO3 ((uint32_t)1U << 4U)
|
||||
#define PUEN3_PUEN_QSPI0_IO2 ((uint32_t)1U << 3U)
|
||||
#define PUEN3_PUEN_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
|
||||
#define PUEN3_PUEN_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
|
||||
#define PUEN3_PUEN_QSPI0_SPCLK ((uint32_t)1U << 0U)
|
||||
#define PUEN3_PUEN_DIGRF_CLKOUT BIT(16)
|
||||
#define PUEN3_PUEN_DIGRF_CLKIN BIT(15)
|
||||
#define PUEN3_PUEN_RPC_INT_N BIT(14)
|
||||
#define PUEN3_PUEN_RPC_WP_N BIT(13)
|
||||
#define PUEN3_PUEN_RPC_RESET_N BIT(12)
|
||||
#define PUEN3_PUEN_QSPI1_SSL BIT(11)
|
||||
#define PUEN3_PUEN_QSPI1_IO3 BIT(10)
|
||||
#define PUEN3_PUEN_QSPI1_IO2 BIT(9)
|
||||
#define PUEN3_PUEN_QSPI1_MISO_IO1 BIT(8)
|
||||
#define PUEN3_PUEN_QSPI1_MOSI_IO0 BIT(7)
|
||||
#define PUEN3_PUEN_QSPI1_SPCLK BIT(6)
|
||||
#define PUEN3_PUEN_QSPI0_SSL BIT(5)
|
||||
#define PUEN3_PUEN_QSPI0_IO3 BIT(4)
|
||||
#define PUEN3_PUEN_QSPI0_IO2 BIT(3)
|
||||
#define PUEN3_PUEN_QSPI0_MISO_IO1 BIT(2)
|
||||
#define PUEN3_PUEN_QSPI0_MOSI_IO0 BIT(1)
|
||||
#define PUEN3_PUEN_QSPI0_SPCLK BIT(0)
|
||||
|
||||
#define PUD0_PUD_VI0_CLK ((uint32_t)1U << 31U)
|
||||
#define PUD0_PUD_IRQ0 ((uint32_t)1U << 26U)
|
||||
#define PUD0_PUD_FSCLKST_N ((uint32_t)1U << 25U)
|
||||
#define PUD0_PUD_PRESETOUT_N ((uint32_t)1U << 23U)
|
||||
#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U)
|
||||
#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U)
|
||||
#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U)
|
||||
#define PUD0_PUD_DU_DOTCLKOUT ((uint32_t)1U << 18U)
|
||||
#define PUD0_PUD_DU_DB7 ((uint32_t)1U << 17U)
|
||||
#define PUD0_PUD_DU_DB6 ((uint32_t)1U << 16U)
|
||||
#define PUD0_PUD_DU_DB5 ((uint32_t)1U << 15U)
|
||||
#define PUD0_PUD_DU_DB4 ((uint32_t)1U << 14U)
|
||||
#define PUD0_PUD_DU_DB3 ((uint32_t)1U << 13U)
|
||||
#define PUD0_PUD_DU_DB2 ((uint32_t)1U << 12U)
|
||||
#define PUD0_PUD_DU_DG7 ((uint32_t)1U << 11U)
|
||||
#define PUD0_PUD_DU_DG6 ((uint32_t)1U << 10U)
|
||||
#define PUD0_PUD_DU_DG5 ((uint32_t)1U << 9U)
|
||||
#define PUD0_PUD_DU_DG4 ((uint32_t)1U << 8U)
|
||||
#define PUD0_PUD_DU_DG3 ((uint32_t)1U << 7U)
|
||||
#define PUD0_PUD_DU_DG2 ((uint32_t)1U << 6U)
|
||||
#define PUD0_PUD_DU_DR7 ((uint32_t)1U << 5U)
|
||||
#define PUD0_PUD_DU_DR6 ((uint32_t)1U << 4U)
|
||||
#define PUD0_PUD_DU_DR5 ((uint32_t)1U << 3U)
|
||||
#define PUD0_PUD_DU_DR4 ((uint32_t)1U << 2U)
|
||||
#define PUD0_PUD_DU_DR3 ((uint32_t)1U << 1U)
|
||||
#define PUD0_PUD_DU_DR2 ((uint32_t)1U << 0U)
|
||||
#define PUD0_PUD_VI0_CLK BIT(31)
|
||||
#define PUD0_PUD_IRQ0 BIT(26)
|
||||
#define PUD0_PUD_FSCLKST_N BIT(25)
|
||||
#define PUD0_PUD_PRESETOUT_N BIT(23)
|
||||
#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
|
||||
#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC BIT(20)
|
||||
#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC BIT(19)
|
||||
#define PUD0_PUD_DU_DOTCLKOUT BIT(18)
|
||||
#define PUD0_PUD_DU_DB7 BIT(17)
|
||||
#define PUD0_PUD_DU_DB6 BIT(16)
|
||||
#define PUD0_PUD_DU_DB5 BIT(15)
|
||||
#define PUD0_PUD_DU_DB4 BIT(14)
|
||||
#define PUD0_PUD_DU_DB3 BIT(13)
|
||||
#define PUD0_PUD_DU_DB2 BIT(12)
|
||||
#define PUD0_PUD_DU_DG7 BIT(11)
|
||||
#define PUD0_PUD_DU_DG6 BIT(10)
|
||||
#define PUD0_PUD_DU_DG5 BIT(9)
|
||||
#define PUD0_PUD_DU_DG4 BIT(8)
|
||||
#define PUD0_PUD_DU_DG3 BIT(7)
|
||||
#define PUD0_PUD_DU_DG2 BIT(6)
|
||||
#define PUD0_PUD_DU_DR7 BIT(5)
|
||||
#define PUD0_PUD_DU_DR6 BIT(4)
|
||||
#define PUD0_PUD_DU_DR5 BIT(3)
|
||||
#define PUD0_PUD_DU_DR4 BIT(2)
|
||||
#define PUD0_PUD_DU_DR3 BIT(1)
|
||||
#define PUD0_PUD_DU_DR2 BIT(0)
|
||||
|
||||
#define PUD1_PUD_VI1_DATA11 ((uint32_t)1U << 31U)
|
||||
#define PUD1_PUD_VI1_DATA10 ((uint32_t)1U << 30U)
|
||||
#define PUD1_PUD_VI1_DATA9 ((uint32_t)1U << 29U)
|
||||
#define PUD1_PUD_VI1_DATA8 ((uint32_t)1U << 28U)
|
||||
#define PUD1_PUD_VI1_DATA7 ((uint32_t)1U << 27U)
|
||||
#define PUD1_PUD_VI1_DATA6 ((uint32_t)1U << 26U)
|
||||
#define PUD1_PUD_VI1_DATA5 ((uint32_t)1U << 25U)
|
||||
#define PUD1_PUD_VI1_DATA4 ((uint32_t)1U << 24U)
|
||||
#define PUD1_PUD_VI1_DATA3 ((uint32_t)1U << 23U)
|
||||
#define PUD1_PUD_VI1_DATA2 ((uint32_t)1U << 22U)
|
||||
#define PUD1_PUD_VI1_DATA1 ((uint32_t)1U << 21U)
|
||||
#define PUD1_PUD_VI1_DATA0 ((uint32_t)1U << 20U)
|
||||
#define PUD1_PUD_VI1_VSYNC_N ((uint32_t)1U << 19U)
|
||||
#define PUD1_PUD_VI1_HSYNC_N ((uint32_t)1U << 18U)
|
||||
#define PUD1_PUD_VI1_CLKENB ((uint32_t)1U << 17U)
|
||||
#define PUD1_PUD_VI1_CLK ((uint32_t)1U << 16U)
|
||||
#define PUD1_PUD_VI0_FIELD ((uint32_t)1U << 15U)
|
||||
#define PUD1_PUD_VI0_DATA11 ((uint32_t)1U << 14U)
|
||||
#define PUD1_PUD_VI0_DATA10 ((uint32_t)1U << 13U)
|
||||
#define PUD1_PUD_VI0_DATA9 ((uint32_t)1U << 12U)
|
||||
#define PUD1_PUD_VI0_DATA8 ((uint32_t)1U << 11U)
|
||||
#define PUD1_PUD_VI0_DATA7 ((uint32_t)1U << 10U)
|
||||
#define PUD1_PUD_VI0_DATA6 ((uint32_t)1U << 9U)
|
||||
#define PUD1_PUD_VI0_DATA5 ((uint32_t)1U << 8U)
|
||||
#define PUD1_PUD_VI0_DATA4 ((uint32_t)1U << 7U)
|
||||
#define PUD1_PUD_VI0_DATA3 ((uint32_t)1U << 6U)
|
||||
#define PUD1_PUD_VI0_DATA2 ((uint32_t)1U << 5U)
|
||||
#define PUD1_PUD_VI0_DATA1 ((uint32_t)1U << 4U)
|
||||
#define PUD1_PUD_VI0_DATA0 ((uint32_t)1U << 3U)
|
||||
#define PUD1_PUD_VI0_VSYNC_N ((uint32_t)1U << 2U)
|
||||
#define PUD1_PUD_VI0_HSYNC_N ((uint32_t)1U << 1U)
|
||||
#define PUD1_PUD_VI0_CLKENB ((uint32_t)1U << 0U)
|
||||
#define PUD1_PUD_VI1_DATA11 BIT(31)
|
||||
#define PUD1_PUD_VI1_DATA10 BIT(30)
|
||||
#define PUD1_PUD_VI1_DATA9 BIT(29)
|
||||
#define PUD1_PUD_VI1_DATA8 BIT(28)
|
||||
#define PUD1_PUD_VI1_DATA7 BIT(27)
|
||||
#define PUD1_PUD_VI1_DATA6 BIT(26)
|
||||
#define PUD1_PUD_VI1_DATA5 BIT(25)
|
||||
#define PUD1_PUD_VI1_DATA4 BIT(24)
|
||||
#define PUD1_PUD_VI1_DATA3 BIT(23)
|
||||
#define PUD1_PUD_VI1_DATA2 BIT(22)
|
||||
#define PUD1_PUD_VI1_DATA1 BIT(21)
|
||||
#define PUD1_PUD_VI1_DATA0 BIT(20)
|
||||
#define PUD1_PUD_VI1_VSYNC_N BIT(19)
|
||||
#define PUD1_PUD_VI1_HSYNC_N BIT(18)
|
||||
#define PUD1_PUD_VI1_CLKENB BIT(17)
|
||||
#define PUD1_PUD_VI1_CLK BIT(16)
|
||||
#define PUD1_PUD_VI0_FIELD BIT(15)
|
||||
#define PUD1_PUD_VI0_DATA11 BIT(14)
|
||||
#define PUD1_PUD_VI0_DATA10 BIT(13)
|
||||
#define PUD1_PUD_VI0_DATA9 BIT(12)
|
||||
#define PUD1_PUD_VI0_DATA8 BIT(11)
|
||||
#define PUD1_PUD_VI0_DATA7 BIT(10)
|
||||
#define PUD1_PUD_VI0_DATA6 BIT(9)
|
||||
#define PUD1_PUD_VI0_DATA5 BIT(8)
|
||||
#define PUD1_PUD_VI0_DATA4 BIT(7)
|
||||
#define PUD1_PUD_VI0_DATA3 BIT(6)
|
||||
#define PUD1_PUD_VI0_DATA2 BIT(5)
|
||||
#define PUD1_PUD_VI0_DATA1 BIT(4)
|
||||
#define PUD1_PUD_VI0_DATA0 BIT(3)
|
||||
#define PUD1_PUD_VI0_VSYNC_N BIT(2)
|
||||
#define PUD1_PUD_VI0_HSYNC_N BIT(1)
|
||||
#define PUD1_PUD_VI0_CLKENB BIT(0)
|
||||
|
||||
#define PUD2_PUD_CANFD_CLK ((uint32_t)1U << 31U)
|
||||
#define PUD2_PUD_CANFD1_RX ((uint32_t)1U << 30U)
|
||||
#define PUD2_PUD_CANFD1_TX ((uint32_t)1U << 29U)
|
||||
#define PUD2_PUD_CANFD0_RX ((uint32_t)1U << 28U)
|
||||
#define PUD2_PUD_CANFD0_TX ((uint32_t)1U << 27U)
|
||||
#define PUD2_PUD_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U)
|
||||
#define PUD2_PUD_AVB0_AVTP_MATCH ((uint32_t)1U << 25U)
|
||||
#define PUD2_PUD_AVB0_LINK ((uint32_t)1U << 24U)
|
||||
#define PUD2_PUD_AVB0_PHY_INT ((uint32_t)1U << 23U)
|
||||
#define PUD2_PUD_AVB0_MAGIC ((uint32_t)1U << 22U)
|
||||
#define PUD2_PUD_AVB0_MDC ((uint32_t)1U << 21U)
|
||||
#define PUD2_PUD_AVB0_MDIO ((uint32_t)1U << 20U)
|
||||
#define PUD2_PUD_AVB0_TXCREFCLK ((uint32_t)1U << 19U)
|
||||
#define PUD2_PUD_AVB0_TD3 ((uint32_t)1U << 18U)
|
||||
#define PUD2_PUD_AVB0_TD2 ((uint32_t)1U << 17U)
|
||||
#define PUD2_PUD_AVB0_TD1 ((uint32_t)1U << 16U)
|
||||
#define PUD2_PUD_AVB0_TD0 ((uint32_t)1U << 15U)
|
||||
#define PUD2_PUD_AVB0_TXC ((uint32_t)1U << 14U)
|
||||
#define PUD2_PUD_AVB0_TX_CTL ((uint32_t)1U << 13U)
|
||||
#define PUD2_PUD_AVB0_RD3 ((uint32_t)1U << 12U)
|
||||
#define PUD2_PUD_AVB0_RD2 ((uint32_t)1U << 11U)
|
||||
#define PUD2_PUD_AVB0_RD1 ((uint32_t)1U << 10U)
|
||||
#define PUD2_PUD_AVB0_RD0 ((uint32_t)1U << 9U)
|
||||
#define PUD2_PUD_AVB0_RXC ((uint32_t)1U << 8U)
|
||||
#define PUD2_PUD_AVB0_RX_CTL ((uint32_t)1U << 7U)
|
||||
#define PUD2_PUD_SDA2 ((uint32_t)1U << 6U)
|
||||
#define PUD2_PUD_SCL2 ((uint32_t)1U << 5U)
|
||||
#define PUD2_PUD_SDA1 ((uint32_t)1U << 4U)
|
||||
#define PUD2_PUD_SCL1 ((uint32_t)1U << 3U)
|
||||
#define PUD2_PUD_SDA0 ((uint32_t)1U << 2U)
|
||||
#define PUD2_PUD_SCL0 ((uint32_t)1U << 1U)
|
||||
#define PUD2_PUD_VI1_FIELD ((uint32_t)1U << 0U)
|
||||
#define PUD2_PUD_CANFD_CLK BIT(31)
|
||||
#define PUD2_PUD_CANFD1_RX BIT(30)
|
||||
#define PUD2_PUD_CANFD1_TX BIT(29)
|
||||
#define PUD2_PUD_CANFD0_RX BIT(28)
|
||||
#define PUD2_PUD_CANFD0_TX BIT(27)
|
||||
#define PUD2_PUD_AVB0_AVTP_CAPTURE BIT(26)
|
||||
#define PUD2_PUD_AVB0_AVTP_MATCH BIT(25)
|
||||
#define PUD2_PUD_AVB0_LINK BIT(24)
|
||||
#define PUD2_PUD_AVB0_PHY_INT BIT(23)
|
||||
#define PUD2_PUD_AVB0_MAGIC BIT(22)
|
||||
#define PUD2_PUD_AVB0_MDC BIT(21)
|
||||
#define PUD2_PUD_AVB0_MDIO BIT(20)
|
||||
#define PUD2_PUD_AVB0_TXCREFCLK BIT(19)
|
||||
#define PUD2_PUD_AVB0_TD3 BIT(18)
|
||||
#define PUD2_PUD_AVB0_TD2 BIT(17)
|
||||
#define PUD2_PUD_AVB0_TD1 BIT(16)
|
||||
#define PUD2_PUD_AVB0_TD0 BIT(15)
|
||||
#define PUD2_PUD_AVB0_TXC BIT(14)
|
||||
#define PUD2_PUD_AVB0_TX_CTL BIT(13)
|
||||
#define PUD2_PUD_AVB0_RD3 BIT(12)
|
||||
#define PUD2_PUD_AVB0_RD2 BIT(11)
|
||||
#define PUD2_PUD_AVB0_RD1 BIT(10)
|
||||
#define PUD2_PUD_AVB0_RD0 BIT(9)
|
||||
#define PUD2_PUD_AVB0_RXC BIT(8)
|
||||
#define PUD2_PUD_AVB0_RX_CTL BIT(7)
|
||||
#define PUD2_PUD_SDA2 BIT(6)
|
||||
#define PUD2_PUD_SCL2 BIT(5)
|
||||
#define PUD2_PUD_SDA1 BIT(4)
|
||||
#define PUD2_PUD_SCL1 BIT(3)
|
||||
#define PUD2_PUD_SDA0 BIT(2)
|
||||
#define PUD2_PUD_SCL0 BIT(1)
|
||||
#define PUD2_PUD_VI1_FIELD BIT(0)
|
||||
|
||||
#define PUD3_PUD_DIGRF_CLKOUT ((uint32_t)1U << 16U)
|
||||
#define PUD3_PUD_DIGRF_CLKIN ((uint32_t)1U << 15U)
|
||||
#define PUD3_PUD_RPC_INT_N ((uint32_t)1U << 14U)
|
||||
#define PUD3_PUD_RPC_WP_N ((uint32_t)1U << 13U)
|
||||
#define PUD3_PUD_RPC_RESET_N ((uint32_t)1U << 12U)
|
||||
#define PUD3_PUD_QSPI1_SSL ((uint32_t)1U << 11U)
|
||||
#define PUD3_PUD_QSPI1_IO3 ((uint32_t)1U << 10U)
|
||||
#define PUD3_PUD_QSPI1_IO2 ((uint32_t)1U << 9U)
|
||||
#define PUD3_PUD_QSPI1_MISO_IO1 ((uint32_t)1U << 8U)
|
||||
#define PUD3_PUD_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U)
|
||||
#define PUD3_PUD_QSPI1_SPCLK ((uint32_t)1U << 6U)
|
||||
#define PUD3_PUD_QSPI0_SSL ((uint32_t)1U << 5U)
|
||||
#define PUD3_PUD_QSPI0_IO3 ((uint32_t)1U << 4U)
|
||||
#define PUD3_PUD_QSPI0_IO2 ((uint32_t)1U << 3U)
|
||||
#define PUD3_PUD_QSPI0_MISO_IO1 ((uint32_t)1U << 2U)
|
||||
#define PUD3_PUD_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U)
|
||||
#define PUD3_PUD_QSPI0_SPCLK ((uint32_t)1U << 0U)
|
||||
#define PUD3_PUD_DIGRF_CLKOUT BIT(16)
|
||||
#define PUD3_PUD_DIGRF_CLKIN BIT(15)
|
||||
#define PUD3_PUD_RPC_INT_N BIT(14)
|
||||
#define PUD3_PUD_RPC_WP_N BIT(13)
|
||||
#define PUD3_PUD_RPC_RESET_N BIT(12)
|
||||
#define PUD3_PUD_QSPI1_SSL BIT(11)
|
||||
#define PUD3_PUD_QSPI1_IO3 BIT(10)
|
||||
#define PUD3_PUD_QSPI1_IO2 BIT(9)
|
||||
#define PUD3_PUD_QSPI1_MISO_IO1 BIT(8)
|
||||
#define PUD3_PUD_QSPI1_MOSI_IO0 BIT(7)
|
||||
#define PUD3_PUD_QSPI1_SPCLK BIT(6)
|
||||
#define PUD3_PUD_QSPI0_SSL BIT(5)
|
||||
#define PUD3_PUD_QSPI0_IO3 BIT(4)
|
||||
#define PUD3_PUD_QSPI0_IO2 BIT(3)
|
||||
#define PUD3_PUD_QSPI0_MISO_IO1 BIT(2)
|
||||
#define PUD3_PUD_QSPI0_MOSI_IO0 BIT(1)
|
||||
#define PUD3_PUD_QSPI0_SPCLK BIT(0)
|
||||
|
||||
#define MOD_SEL0_sel_hscif0 ((uint32_t)1U << 10U)
|
||||
#define MOD_SEL0_sel_scif1 ((uint32_t)1U << 9U)
|
||||
#define MOD_SEL0_sel_canfd0 ((uint32_t)1U << 8U)
|
||||
#define MOD_SEL0_sel_pwm4 ((uint32_t)1U << 7U)
|
||||
#define MOD_SEL0_sel_pwm3 ((uint32_t)1U << 6U)
|
||||
#define MOD_SEL0_sel_pwm2 ((uint32_t)1U << 5U)
|
||||
#define MOD_SEL0_sel_pwm1 ((uint32_t)1U << 4U)
|
||||
#define MOD_SEL0_sel_pwm0 ((uint32_t)1U << 3U)
|
||||
#define MOD_SEL0_sel_rfso ((uint32_t)1U << 2U)
|
||||
#define MOD_SEL0_sel_rsp ((uint32_t)1U << 1U)
|
||||
#define MOD_SEL0_sel_tmu ((uint32_t)1U << 0U)
|
||||
#define MOD_SEL0_sel_hscif0 BIT(10)
|
||||
#define MOD_SEL0_sel_scif1 BIT(9)
|
||||
#define MOD_SEL0_sel_canfd0 BIT(8)
|
||||
#define MOD_SEL0_sel_pwm4 BIT(7)
|
||||
#define MOD_SEL0_sel_pwm3 BIT(6)
|
||||
#define MOD_SEL0_sel_pwm2 BIT(5)
|
||||
#define MOD_SEL0_sel_pwm1 BIT(4)
|
||||
#define MOD_SEL0_sel_pwm0 BIT(3)
|
||||
#define MOD_SEL0_sel_rfso BIT(2)
|
||||
#define MOD_SEL0_sel_rsp BIT(1)
|
||||
#define MOD_SEL0_sel_tmu BIT(0)
|
||||
|
||||
/* SCIF3 Registers for Dummy write */
|
||||
#define SCIF3_BASE (0xE6C50000U)
|
||||
|
|
@ -502,7 +502,7 @@ static void StartRtDma0_Descriptor(void)
|
|||
}
|
||||
|
||||
/* Initialize ch0, Reset Descriptor */
|
||||
mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t)1U << RTDMAC_CH));
|
||||
mmio_write_32(RTDMAC_RDMCHCLR, BIT(RTDMAC_CH));
|
||||
mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
|
||||
|
||||
/* Enable DMA */
|
||||
|
|
|
|||
Loading…
Reference in New Issue