Merge pull request #1882 from ambroise-arm/av/a15-errata
Apply workarounds for errata of Cortex-A15
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b9d20d0eda
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@ -71,6 +71,14 @@ for it to specify which errata workarounds should be enabled or not.
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The value of the build flags is 0 by default, that is, disabled. A value of 1
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will enable it.
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For Cortex-A15, the following errata build flags are defined :
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- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
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CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
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- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
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CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
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For Cortex-A53, the following errata build flags are defined :
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- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
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@ -9,6 +9,13 @@
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Auxiliary Control Register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4
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#define CORTEX_A15_ACTLR2_INV_DCC_BIT (U(1) << 0)
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/*******************************************************************************
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* Cortex-A15 midr with version/revision set to 0
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******************************************************************************/
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -29,6 +29,13 @@ func cortex_a15_disable_smp
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bic r0, #CORTEX_A15_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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#if ERRATA_A15_816470
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/*
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* Invalidate any TLB address
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*/
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mov r0, #0
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stcopr r0, TLBIMVA
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#endif
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dsb sy
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bx lr
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endfunc cortex_a15_disable_smp
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@ -41,6 +48,49 @@ func cortex_a15_enable_smp
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bx lr
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endfunc cortex_a15_enable_smp
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A15 Errata #816470.
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* This applies only to revision >= r3p0 of Cortex A15.
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* ----------------------------------------------------
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*/
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func check_errata_816470
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/*
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* Even though this is only needed for revision >= r3p0, it is always
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* applied because of the low cost of the workaround.
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*/
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mov r0, #ERRATA_APPLIES
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bx lr
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endfunc check_errata_816470
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A15 Errata #827671.
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* This applies only to revision >= r3p0 of Cortex A15.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ----------------------------------------------------
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*/
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func errata_a15_827671_wa
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/*
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* Compare r0 against revision r3p0
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*/
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mov r2, lr
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bl check_errata_827671
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr r0, CORTEX_A15_ACTLR2
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orr r0, #CORTEX_A15_ACTLR2_INV_DCC_BIT
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stcopr r0, CORTEX_A15_ACTLR2
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isb
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1:
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bx r2
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endfunc errata_a15_827671_wa
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func check_errata_827671
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mov r1, #0x30
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b cpu_rev_var_hs
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endfunc check_errata_827671
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func check_errata_cve_2017_5715
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#if WORKAROUND_CVE_2017_5715
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mov r0, #ERRATA_APPLIES
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@ -64,6 +114,8 @@ func cortex_a15_errata_report
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A15_816470, cortex_a15, 816470
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report_errata ERRATA_A15_827671, cortex_a15, 827671
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report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715
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pop {r12, lr}
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@ -72,6 +124,13 @@ endfunc cortex_a15_errata_report
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#endif
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func cortex_a15_reset_func
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mov r5, lr
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bl cpu_get_rev_var
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#if ERRATA_A15_827671
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bl errata_a15_827671_wa
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#endif
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#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A15_ACTLR_INV_BTB_BIT
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@ -81,6 +140,8 @@ func cortex_a15_reset_func
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stcopr r0, MVBAR
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/* isb will be applied in the course of the reset func */
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#endif
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mov lr, r5
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b cortex_a15_enable_smp
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endfunc cortex_a15_reset_func
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@ -53,6 +53,14 @@ endif
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# These should be enabled by the platform if the erratum workaround needs to be
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# applied.
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# Flag to apply erratum 816470 workaround during power down. This erratum
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# applies only to revision >= r3p0 of the Cortex A15 cpu.
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ERRATA_A15_816470 ?=0
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# Flag to apply erratum 827671 workaround during reset. This erratum applies
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# only to revision >= r3p0 of the Cortex A15 cpu.
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ERRATA_A15_827671 ?=0
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# Flag to apply erratum 819472 workaround during reset. This erratum applies
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# only to revision <= r0p1 of the Cortex A53 cpu.
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ERRATA_A53_819472 ?=0
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@ -196,6 +204,14 @@ ERRATA_N1_1043202 ?=1
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# higher DSU power consumption on idle.
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ERRATA_DSU_936184 ?=0
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# Process ERRATA_A15_816470 flag
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$(eval $(call assert_boolean,ERRATA_A15_816470))
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$(eval $(call add_define,ERRATA_A15_816470))
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# Process ERRATA_A15_827671 flag
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$(eval $(call assert_boolean,ERRATA_A15_827671))
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$(eval $(call add_define,ERRATA_A15_827671))
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# Process ERRATA_A53_819472 flag
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$(eval $(call assert_boolean,ERRATA_A53_819472))
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$(eval $(call add_define,ERRATA_A53_819472))
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