commit
ba91a001f8
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -19,28 +19,6 @@
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/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
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/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
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#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1
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#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7
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#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6
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#define CPUAMCFGR_EL0 S3_3_C15_C10_6
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#define CPUAMUSERENR_EL0 S3_3_C15_C10_7
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/* Activity Monitor Event Counter Registers */
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#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0
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#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1
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#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2
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#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3
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#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4
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/* Activity Monitor Event Type Registers */
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#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0
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#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1
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#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2
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#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3
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#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4
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#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
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#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
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/*
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/*
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@ -50,9 +28,9 @@
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* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
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* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
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* enable this with suitable programming.
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* enable this with suitable programming.
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*/
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*/
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#define CORTEX_A75_AMU_NR_COUNTERS 5
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#define CORTEX_A75_AMU_NR_COUNTERS U(5)
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#define CORTEX_A75_AMU_GROUP0_MASK 0x7
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#define CORTEX_A75_AMU_GROUP0_MASK U(0x7)
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#define CORTEX_A75_AMU_GROUP1_MASK (0 << 3)
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#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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#include <stdint.h>
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@ -0,0 +1,48 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CPUAMU_H__
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#define __CPUAMU_H__
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7
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#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6
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#define CPUAMCFGR_EL0 S3_3_C15_C10_6
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#define CPUAMUSERENR_EL0 S3_3_C15_C10_7
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/* Activity Monitor Event Counter Registers */
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#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0
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#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1
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#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2
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#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3
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#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4
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/* Activity Monitor Event Type Registers */
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#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0
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#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1
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#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2
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#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3
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#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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uint64_t cpuamu_cnt_read(int idx);
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void cpuamu_cnt_write(int idx, uint64_t val);
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unsigned int cpuamu_read_cpuamcntenset_el0(void);
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unsigned int cpuamu_read_cpuamcntenclr_el0(void);
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void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
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void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
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int midr_match(unsigned int cpu_midr);
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void cpuamu_context_save(unsigned int nr_counters);
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void cpuamu_context_restore(unsigned int nr_counters);
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#endif /* __ASSEMBLY__ */
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#endif /* __CPUAMU_H__ */
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@ -6,108 +6,9 @@
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#include <arch.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include <cortex_a75.h>
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#include <cortex_a75.h>
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#include <cpuamu.h>
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.globl cortex_a75_amu_cnt_read
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#include <cpu_macros.S>
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.globl cortex_a75_amu_cnt_write
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.globl cortex_a75_amu_read_cpuamcntenset_el0
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.globl cortex_a75_amu_read_cpuamcntenclr_el0
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.globl cortex_a75_amu_write_cpuamcntenset_el0
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.globl cortex_a75_amu_write_cpuamcntenclr_el0
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/*
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* uint64_t cortex_a75_amu_cnt_read(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `x0`.
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*/
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func cortex_a75_amu_cnt_read
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adr x1, 1f
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lsl x0, x0, #3
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add x1, x1, x0
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br x1
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1:
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mrs x0, CPUAMEVCNTR0_EL0
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ret
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mrs x0, CPUAMEVCNTR1_EL0
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ret
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mrs x0, CPUAMEVCNTR2_EL0
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ret
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mrs x0, CPUAMEVCNTR3_EL0
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ret
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mrs x0, CPUAMEVCNTR4_EL0
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ret
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endfunc cortex_a75_amu_cnt_read
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/*
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* void cortex_a75_amu_cnt_write(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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*/
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func cortex_a75_amu_cnt_write
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adr x2, 1f
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lsl x0, x0, #3
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add x2, x2, x0
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br x2
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1:
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msr CPUAMEVCNTR0_EL0, x0
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ret
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msr CPUAMEVCNTR1_EL0, x0
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ret
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msr CPUAMEVCNTR2_EL0, x0
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ret
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msr CPUAMEVCNTR3_EL0, x0
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ret
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msr CPUAMEVCNTR4_EL0, x0
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ret
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endfunc cortex_a75_amu_cnt_write
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/*
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* unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void);
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*
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* Read the `CPUAMCNTENSET_EL0` CPU register and return
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* it in `x0`.
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*/
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func cortex_a75_amu_read_cpuamcntenset_el0
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mrs x0, CPUAMCNTENSET_EL0
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ret
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endfunc cortex_a75_amu_read_cpuamcntenset_el0
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/*
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* unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void);
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*
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* Read the `CPUAMCNTENCLR_EL0` CPU register and return
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* it in `x0`.
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*/
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func cortex_a75_amu_read_cpuamcntenclr_el0
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mrs x0, CPUAMCNTENCLR_EL0
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ret
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endfunc cortex_a75_amu_read_cpuamcntenclr_el0
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/*
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* void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
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*
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* Write `mask` to the `CPUAMCNTENSET_EL0` CPU register.
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*/
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func cortex_a75_amu_write_cpuamcntenset_el0
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msr CPUAMCNTENSET_EL0, x0
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ret
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endfunc cortex_a75_amu_write_cpuamcntenset_el0
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/*
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* void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
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*
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* Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register.
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*/
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func cortex_a75_amu_write_cpuamcntenclr_el0
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mrs x0, CPUAMCNTENCLR_EL0
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ret
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endfunc cortex_a75_amu_write_cpuamcntenclr_el0
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func cortex_a75_reset_func
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func cortex_a75_reset_func
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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@ -1,73 +1,24 @@
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/*
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/*
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||||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
|
*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
|
*/
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#include <cortex_a75.h>
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#include <cortex_a75.h>
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#include <platform.h>
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#include <cpuamu.h>
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#include <pubsub_events.h>
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#include <pubsub_events.h>
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struct amu_ctx {
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uint64_t cnts[CORTEX_A75_AMU_NR_COUNTERS];
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uint16_t mask;
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};
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static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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static void *cortex_a75_context_save(const void *arg)
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static void *cortex_a75_context_save(const void *arg)
|
||||||
{
|
{
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||||||
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
if (midr_match(CORTEX_A75_MIDR) != 0)
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unsigned int midr;
|
cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS);
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unsigned int midr_mask;
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int i;
|
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|
|
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midr = read_midr();
|
|
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midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
|
|
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(MIDR_PN_MASK << MIDR_PN_SHIFT);
|
|
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if ((midr & midr_mask) != (CORTEX_A75_MIDR & midr_mask))
|
|
||||||
return 0;
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|
||||||
|
|
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/* Save counter configuration */
|
|
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ctx->mask = cortex_a75_amu_read_cpuamcntenset_el0();
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||||||
|
|
||||||
/* Ensure counters are disabled */
|
|
||||||
cortex_a75_amu_write_cpuamcntenclr_el0(ctx->mask);
|
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||||||
isb();
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||||||
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|
||||||
/* Save counters */
|
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||||||
for (i = 0; i < CORTEX_A75_AMU_NR_COUNTERS; i++)
|
|
||||||
ctx->cnts[i] = cortex_a75_amu_cnt_read(i);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void *cortex_a75_context_restore(const void *arg)
|
static void *cortex_a75_context_restore(const void *arg)
|
||||||
{
|
{
|
||||||
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
if (midr_match(CORTEX_A75_MIDR) != 0)
|
||||||
unsigned int midr;
|
cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS);
|
||||||
unsigned int midr_mask;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
midr = read_midr();
|
|
||||||
midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
|
|
||||||
(MIDR_PN_MASK << MIDR_PN_SHIFT);
|
|
||||||
if ((midr & midr_mask) != (CORTEX_A75_MIDR & midr_mask))
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
ctx = &amu_ctxs[plat_my_core_pos()];
|
|
||||||
|
|
||||||
/* Counters were disabled in `cortex_a75_context_save()` */
|
|
||||||
assert(cortex_a75_amu_read_cpuamcntenset_el0() == 0);
|
|
||||||
|
|
||||||
/* Restore counters */
|
|
||||||
for (i = 0; i < CORTEX_A75_AMU_NR_COUNTERS; i++)
|
|
||||||
cortex_a75_amu_cnt_write(i, ctx->cnts[i]);
|
|
||||||
isb();
|
|
||||||
|
|
||||||
/* Restore counter configuration */
|
|
||||||
cortex_a75_amu_write_cpuamcntenset_el0(ctx->mask);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,70 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <cpuamu.h>
|
||||||
|
#include <platform.h>
|
||||||
|
#include <pubsub_events.h>
|
||||||
|
|
||||||
|
#define CPUAMU_NR_COUNTERS 5U
|
||||||
|
|
||||||
|
struct amu_ctx {
|
||||||
|
uint64_t cnts[CPUAMU_NR_COUNTERS];
|
||||||
|
unsigned int mask;
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
|
||||||
|
|
||||||
|
int midr_match(unsigned int cpu_midr)
|
||||||
|
{
|
||||||
|
unsigned int midr, midr_mask;
|
||||||
|
|
||||||
|
midr = (unsigned int)read_midr();
|
||||||
|
midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
|
||||||
|
(MIDR_PN_MASK << MIDR_PN_SHIFT);
|
||||||
|
return ((midr & midr_mask) == (cpu_midr & midr_mask));
|
||||||
|
}
|
||||||
|
|
||||||
|
void cpuamu_context_save(unsigned int nr_counters)
|
||||||
|
{
|
||||||
|
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
assert(nr_counters <= CPUAMU_NR_COUNTERS);
|
||||||
|
|
||||||
|
/* Save counter configuration */
|
||||||
|
ctx->mask = cpuamu_read_cpuamcntenset_el0();
|
||||||
|
|
||||||
|
/* Disable counters */
|
||||||
|
cpuamu_write_cpuamcntenclr_el0(ctx->mask);
|
||||||
|
isb();
|
||||||
|
|
||||||
|
/* Save counters */
|
||||||
|
for (i = 0; i < nr_counters; i++)
|
||||||
|
ctx->cnts[i] = cpuamu_cnt_read(i);
|
||||||
|
}
|
||||||
|
|
||||||
|
void cpuamu_context_restore(unsigned int nr_counters)
|
||||||
|
{
|
||||||
|
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
assert(nr_counters <= CPUAMU_NR_COUNTERS);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Disable counters. They were enabled early in the
|
||||||
|
* CPU reset function.
|
||||||
|
*/
|
||||||
|
cpuamu_write_cpuamcntenclr_el0(ctx->mask);
|
||||||
|
isb();
|
||||||
|
|
||||||
|
/* Restore counters */
|
||||||
|
for (i = 0; i < nr_counters; i++)
|
||||||
|
cpuamu_cnt_write(i, ctx->cnts[i]);
|
||||||
|
isb();
|
||||||
|
|
||||||
|
/* Restore counter configuration */
|
||||||
|
cpuamu_write_cpuamcntenset_el0(ctx->mask);
|
||||||
|
}
|
|
@ -0,0 +1,107 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch.h>
|
||||||
|
#include <asm_macros.S>
|
||||||
|
#include <cpuamu.h>
|
||||||
|
|
||||||
|
.globl cpuamu_cnt_read
|
||||||
|
.globl cpuamu_cnt_write
|
||||||
|
.globl cpuamu_read_cpuamcntenset_el0
|
||||||
|
.globl cpuamu_read_cpuamcntenclr_el0
|
||||||
|
.globl cpuamu_write_cpuamcntenset_el0
|
||||||
|
.globl cpuamu_write_cpuamcntenclr_el0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* uint64_t cpuamu_cnt_read(int idx);
|
||||||
|
*
|
||||||
|
* Given `idx`, read the corresponding AMU counter
|
||||||
|
* and return it in `x0`.
|
||||||
|
*/
|
||||||
|
func cpuamu_cnt_read
|
||||||
|
adr x1, 1f
|
||||||
|
lsl x0, x0, #3
|
||||||
|
add x1, x1, x0
|
||||||
|
br x1
|
||||||
|
|
||||||
|
1:
|
||||||
|
mrs x0, CPUAMEVCNTR0_EL0
|
||||||
|
ret
|
||||||
|
mrs x0, CPUAMEVCNTR1_EL0
|
||||||
|
ret
|
||||||
|
mrs x0, CPUAMEVCNTR2_EL0
|
||||||
|
ret
|
||||||
|
mrs x0, CPUAMEVCNTR3_EL0
|
||||||
|
ret
|
||||||
|
mrs x0, CPUAMEVCNTR4_EL0
|
||||||
|
ret
|
||||||
|
endfunc cpuamu_cnt_read
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void cpuamu_cnt_write(int idx, uint64_t val);
|
||||||
|
*
|
||||||
|
* Given `idx`, write `val` to the corresponding AMU counter.
|
||||||
|
*/
|
||||||
|
func cpuamu_cnt_write
|
||||||
|
adr x2, 1f
|
||||||
|
lsl x0, x0, #3
|
||||||
|
add x2, x2, x0
|
||||||
|
br x2
|
||||||
|
|
||||||
|
1:
|
||||||
|
msr CPUAMEVCNTR0_EL0, x0
|
||||||
|
ret
|
||||||
|
msr CPUAMEVCNTR1_EL0, x0
|
||||||
|
ret
|
||||||
|
msr CPUAMEVCNTR2_EL0, x0
|
||||||
|
ret
|
||||||
|
msr CPUAMEVCNTR3_EL0, x0
|
||||||
|
ret
|
||||||
|
msr CPUAMEVCNTR4_EL0, x0
|
||||||
|
ret
|
||||||
|
endfunc cpuamu_cnt_write
|
||||||
|
|
||||||
|
/*
|
||||||
|
* unsigned int cpuamu_read_cpuamcntenset_el0(void);
|
||||||
|
*
|
||||||
|
* Read the `CPUAMCNTENSET_EL0` CPU register and return
|
||||||
|
* it in `x0`.
|
||||||
|
*/
|
||||||
|
func cpuamu_read_cpuamcntenset_el0
|
||||||
|
mrs x0, CPUAMCNTENSET_EL0
|
||||||
|
ret
|
||||||
|
endfunc cpuamu_read_cpuamcntenset_el0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* unsigned int cpuamu_read_cpuamcntenclr_el0(void);
|
||||||
|
*
|
||||||
|
* Read the `CPUAMCNTENCLR_EL0` CPU register and return
|
||||||
|
* it in `x0`.
|
||||||
|
*/
|
||||||
|
func cpuamu_read_cpuamcntenclr_el0
|
||||||
|
mrs x0, CPUAMCNTENCLR_EL0
|
||||||
|
ret
|
||||||
|
endfunc cpuamu_read_cpuamcntenclr_el0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
|
||||||
|
*
|
||||||
|
* Write `mask` to the `CPUAMCNTENSET_EL0` CPU register.
|
||||||
|
*/
|
||||||
|
func cpuamu_write_cpuamcntenset_el0
|
||||||
|
msr CPUAMCNTENSET_EL0, x0
|
||||||
|
ret
|
||||||
|
endfunc cpuamu_write_cpuamcntenset_el0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
|
||||||
|
*
|
||||||
|
* Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register.
|
||||||
|
*/
|
||||||
|
func cpuamu_write_cpuamcntenclr_el0
|
||||||
|
msr CPUAMCNTENCLR_EL0, x0
|
||||||
|
ret
|
||||||
|
endfunc cpuamu_write_cpuamcntenclr_el0
|
|
@ -182,7 +182,9 @@ ENABLE_PLAT_COMPAT := 0
|
||||||
ENABLE_AMU := 1
|
ENABLE_AMU := 1
|
||||||
|
|
||||||
ifeq (${ENABLE_AMU},1)
|
ifeq (${ENABLE_AMU},1)
|
||||||
BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c
|
BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
|
||||||
|
lib/cpus/aarch64/cpuamu.c \
|
||||||
|
lib/cpus/aarch64/cpuamu_helpers.S
|
||||||
endif
|
endif
|
||||||
|
|
||||||
ifneq (${ENABLE_STACK_PROTECTOR},0)
|
ifneq (${ENABLE_STACK_PROTECTOR},0)
|
||||||
|
|
Loading…
Reference in New Issue