fix(intel): refactor NOC header
Refactor NOC header to be shareable across both Stratix 10 and Agilex platforms. This patch also removes redundant NOC declarations in system manager header file. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I6348b67a8b54c2ad19327d6b8c25ae37d25e4b4a Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This commit is contained in:
Abdul Halim, Muhammad Hadi Asyrafi
Sieu Mun Tang
parent
19a9cc3a1b
commit
bc1a573d55
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -19,6 +19,8 @@
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
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/* Register Mapping */
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#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
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#define SOCFPGA_MMC_REG_BASE 0xff808000
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#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
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/*
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_NOC_H
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#define SOCFPGA_NOC_H
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/* Macros */
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#define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \
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+ (SOCFPGA_CCU_NOC_##_ctrl##_##_dev))
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#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \
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+ (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
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#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
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+ (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
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/* L3 Interconnect Register Map */
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#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000
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#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004
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#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040
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#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044
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#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068
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#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
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/* CCU NOC Register Map */
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#define SOCFPGA_CCU_NOC_CPU0_RAM0 0x04688
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#define SOCFPGA_CCU_NOC_IOM_RAM0 0x18628
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#define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0)
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#define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1)
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#endif
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@ -58,67 +58,6 @@
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#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
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+ (SOCFPGA_SYSMGR_##_reg))
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#define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \
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+ (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
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#define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \
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+ (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
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/* L3 Interconnect Register Map */
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#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000
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#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004
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#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030
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#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040
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#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044
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#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064
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#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068
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#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c
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#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090
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#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
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#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
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#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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void enable_ns_peripheral_access(void);
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void enable_ns_bridge_access(void);
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include "socfpga_noc.h"
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#include "socfpga_system_manager.h"
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void enable_nonsecure_access(void)
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@ -92,10 +93,10 @@ void enable_ns_peripheral_access(void)
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mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL);
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#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
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mmio_clrbits_32(SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
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mmio_clrbits_32(SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
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mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3));
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mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0),
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SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK);
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mmio_clrbits_32(SOCFPGA_CCU_NOC(IOM, RAM0),
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SOCFPGA_CCU_NOC_ADMASK_P_MASK | SOCFPGA_CCU_NOC_ADMASK_NS_MASK);
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#endif
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}
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@ -1,5 +1,4 @@
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/*
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -19,6 +18,8 @@
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#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000
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/* Register Mapping */
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#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
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#define SOCFPGA_MMC_REG_BASE 0xff808000
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#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
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