Merge changes I684d54a7,I61339fc5,Ic0dabf3e,Ief09a841 into integration
* changes: feat(plat/rcar): change process for Suspend To RAM fix(plat/rcar): change process that copy code to system ram fix(plat/rcar): fix cache maintenance process of reading cert header fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled
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bf63dc56b0
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@ -380,7 +380,7 @@ static int32_t load_bl33x(void)
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static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
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{
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uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {0UL};
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static uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {0UL};
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uintptr_t handle;
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ssize_t offset;
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uint32_t i;
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@ -423,15 +423,17 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
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WARN("Firmware Image Package header failed to seek\n");
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goto error;
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}
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#if RCAR_BL2_DCACHE == 1
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inv_dcache_range((uint64_t) header, sizeof(header));
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#endif
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rc = io_read(handle, (uintptr_t) &header, sizeof(header), &cnt);
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if (rc != IO_SUCCESS) {
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WARN("Firmware Image Package header failed to read\n");
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goto error;
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}
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#if RCAR_BL2_DCACHE == 1
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inv_dcache_range((uint64_t) header, sizeof(header));
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#endif
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rcar_image_number = header[0];
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for (i = 0; i < rcar_image_number + 2; i++) {
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rcar_image_header[i] = header[i * 2 + 1];
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@ -440,6 +442,7 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
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if (rcar_image_number == 0 || rcar_image_number > RCAR_MAX_BL3X_IMAGE) {
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WARN("Firmware Image Package header check failed.\n");
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rc = IO_FAIL;
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goto error;
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}
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@ -448,10 +451,7 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
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WARN("Firmware Image Package header failed to seek cert\n");
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goto error;
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}
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#if RCAR_BL2_DCACHE == 1
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inv_dcache_range(RCAR_SDRAM_certESS,
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RCAR_CERT_SIZE * (2 + rcar_image_number));
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#endif
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rc = io_read(handle, RCAR_SDRAM_certESS,
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RCAR_CERT_SIZE * (2 + rcar_image_number), &cnt);
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if (rc != IO_SUCCESS) {
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@ -459,6 +459,11 @@ static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
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goto error;
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}
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#if RCAR_BL2_DCACHE == 1
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inv_dcache_range(RCAR_SDRAM_certESS,
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RCAR_CERT_SIZE * (2 + rcar_image_number));
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#endif
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rcar_cert_load = RCAR_CERT_LOAD;
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error:
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@ -776,14 +776,14 @@ void rcar_pwrc_code_copy_to_system_ram(void)
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memcpy((void *)sram.base, code.base, code.len);
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flush_dcache_range((uint64_t) sram.base, code.len);
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attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
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ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
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assert(ret == 0);
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/* Invalidate instruction cache */
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plat_invalidate_icache();
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dsb();
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isb();
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attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
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ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
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assert(ret == 0);
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}
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uint32_t rcar_pwrc_get_cluster(void)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -128,11 +128,6 @@ static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)
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rcar_pwrc_clusteroff(mpidr);
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}
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#if RCAR_SYSTEM_SUSPEND
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if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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rcar_pwrc_suspend_to_ram();
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#endif
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}
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static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
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@ -160,6 +155,18 @@ finish:
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rcar_pwr_domain_on_finish(target_state);
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}
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static void __dead2 rcar_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
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{
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#if RCAR_SYSTEM_SUSPEND
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if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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rcar_pwrc_suspend_to_ram();
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#endif
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wfi();
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ERROR("RCAR Power Down: operation not handled.\n");
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panic();
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}
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static void __dead2 rcar_system_off(void)
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{
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#if PMIC_ROHM_BD9571
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@ -292,6 +299,7 @@ static const plat_psci_ops_t rcar_plat_psci_ops = {
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.system_off = rcar_system_off,
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.system_reset = rcar_system_reset,
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.validate_power_state = rcar_validate_power_state,
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.pwr_domain_pwr_down_wfi = rcar_pwr_domain_pwr_down_wfi,
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#if RCAR_SYSTEM_SUSPEND
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.get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
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#endif
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