fix(errata): workaround for Cortex-X2 errata 2081180

Cortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0
and r2p0 of the Cortex-X2 processor core.

Cortex-X2 SDEN: https://developer.arm.com/documentation/SDEN1775100

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I64bed2fd5b7e12932d6de2ae668786e689885188
This commit is contained in:
Bipin Ravi 2022-01-20 00:42:05 -06:00
parent e7ca4433fa
commit c060b5337a
4 changed files with 70 additions and 0 deletions

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@ -458,6 +458,10 @@ For Cortex-X2, the following errata build flags are defined :
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU, it is fixed in r2p1.
- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU, it is fixed in r2p1.
DSU Errata Workarounds
----------------------

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@ -35,4 +35,12 @@
******************************************************************************/
#define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0
/*******************************************************************************
* CPU Implementation Specific Selected Instruction registers
******************************************************************************/
#define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0
#define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1
#define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2
#define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3
#endif /* CORTEX_X2_H */

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@ -141,6 +141,49 @@ func check_errata_2017096
b cpu_rev_var_ls
endfunc check_errata_2017096
/* --------------------------------------------------
* Errata Workaround for Cortex-X2 Errata 2081180.
* This applies to revision r0p0, r1p0 and r2p0
* and is fixed in r2p1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
func errata_x2_2081180_wa
/* Check revision. */
mov x17, x30
bl check_errata_2081180
cbz x0, 1f
/* Apply instruction patching sequence */
ldr x0, =0x3
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
ldr x0, =0xF3A08002
msr CORTEX_X2_IMP_CPUPOR_EL3, x0
ldr x0, =0xFFF0F7FE
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x10002001003FF
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
ldr x0, =0x4
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
ldr x0, =0xBF200000
msr CORTEX_X2_IMP_CPUPOR_EL3, x0
ldr x0, =0xFFEF0000
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x10002001003F3
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
isb
1:
ret x17
endfunc errata_x2_2081180_wa
func check_errata_2081180
/* Applies to r0p0, r1p0 and r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_2081180
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
@ -175,6 +218,7 @@ func cortex_x2_errata_report
report_errata ERRATA_X2_2058056, cortex_x2, 2058056
report_errata ERRATA_X2_2083908, cortex_x2, 2083908
report_errata ERRATA_X2_2017096, cortex_x2, 2017096
report_errata ERRATA_X2_2081180, cortex_x2, 2081180
ldp x8, x30, [sp], #16
ret
@ -212,6 +256,11 @@ func cortex_x2_reset_func
bl errata_x2_2017096_wa
#endif
#if ERRATA_X2_2081180
mov x0, x18
bl errata_x2_2081180_wa
#endif
ret x19
endfunc cortex_x2_reset_func

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@ -512,6 +512,11 @@ ERRATA_X2_2083908 ?=0
# r2p1.
ERRATA_X2_2017096 ?=0
# Flag to apply erratum 2081180 workaround during reset. This erratum applies
# only to revisions r0p0, r1p0 and r2p0 of the Cortex-X2 cpu, it is fixed in
# r2p1.
ERRATA_X2_2081180 ?=0
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@ -953,6 +958,10 @@ $(eval $(call add_define,ERRATA_X2_2083908))
$(eval $(call assert_boolean,ERRATA_X2_2017096))
$(eval $(call add_define,ERRATA_X2_2017096))
# Process ERRATA_X2_2081180 flag
$(eval $(call assert_boolean,ERRATA_X2_2081180))
$(eval $(call add_define,ERRATA_X2_2081180))
# Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))