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Merge pull request #1878 from jts-arm/sctlr 

Apply stricter speculative load restriction
This commit is contained in:
Soby Mathew 2019-03-13 15:32:00 +00:00 committed by GitHub
parent c61a807a4f 02b5794396
commit c0ce16fba3
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 19 additions and 11 deletions
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7
bl2/aarch32/bl2_entrypoint.S
View File

@ -42,12 +42,13 @@ func bl2_entrypoint
stcopr r0, VBAR stcopr r0, VBAR
isb isb
/* ----------------------------------------------------- /* --------------------------------------------------------
* Enable the instruction cache * Enable the instruction cache - disable speculative loads
* ----------------------------------------------------- * --------------------------------------------------------
*/ */
ldcopr r0, SCTLR ldcopr r0, SCTLR
orr r0, r0, #SCTLR_I_BIT orr r0, r0, #SCTLR_I_BIT
bic r0, r0, #SCTLR_DSSBS_BIT
stcopr r0, SCTLR stcopr r0, SCTLR
isb isb

4
bl2/aarch64/bl2_entrypoint.S
View File

@ -41,12 +41,14 @@ func bl2_entrypoint
/* --------------------------------------------- /* ---------------------------------------------
* Enable the instruction cache, stack pointer * Enable the instruction cache, stack pointer
* and data access alignment checks * and data access alignment checks and disable
* speculative loads.
* --------------------------------------------- * ---------------------------------------------
*/ */
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1 mrs x0, sctlr_el1
orr x0, x0, x1 orr x0, x0, x1
bic x0, x0, #SCTLR_DSSBS_BIT
msr sctlr_el1, x0 msr sctlr_el1, x0
isb isb

9
bl2u/aarch32/bl2u_entrypoint.S
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -41,12 +41,13 @@ func bl2u_entrypoint
stcopr r0, VBAR stcopr r0, VBAR
isb isb
/* ----------------------------------------------------- /* --------------------------------------------------------
* Enable the instruction cache * Enable the instruction cache - disable speculative loads
* ----------------------------------------------------- * --------------------------------------------------------
*/ */
ldcopr r0, SCTLR ldcopr r0, SCTLR
orr r0, r0, #SCTLR_I_BIT orr r0, r0, #SCTLR_I_BIT
bic r0, r0, #SCTLR_DSSBS_BIT
stcopr r0, SCTLR stcopr r0, SCTLR
isb isb

6
bl2u/aarch64/bl2u_entrypoint.S
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -38,12 +38,14 @@ func bl2u_entrypoint
/* --------------------------------------------- /* ---------------------------------------------
* Enable the instruction cache, stack pointer * Enable the instruction cache, stack pointer
* and data access alignment checks * and data access alignment checks and disable
* speculative loads.
* --------------------------------------------- * ---------------------------------------------
*/ */
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1 mrs x0, sctlr_el1
orr x0, x0, x1 orr x0, x0, x1
bic x0, x0, #SCTLR_DSSBS_BIT
msr sctlr_el1, x0 msr sctlr_el1, x0
isb isb

4
bl32/tsp/aarch64/tsp_entrypoint.S
View File

@ -63,12 +63,14 @@ func tsp_entrypoint _align=3
/* --------------------------------------------- /* ---------------------------------------------
* Enable the instruction cache, stack pointer * Enable the instruction cache, stack pointer
* and data access alignment checks * and data access alignment checks and disable
* speculative loads.
* --------------------------------------------- * ---------------------------------------------
*/ */
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
mrs x0, sctlr_el1 mrs x0, sctlr_el1
orr x0, x0, x1 orr x0, x0, x1
bic x0, x0, #SCTLR_DSSBS_BIT
msr sctlr_el1, x0 msr sctlr_el1, x0
isb isb