andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

feat(tc): enable MPMM 

This change enables MPMM and adds, to the TC firmware configuration
device tree, the AMU counters representing the "gears" for the
Maximum Power Mitigation Mechanism feature of the Cortex-X2,
Cortex-A710 and Cortex-A510:

- Gear 0: throttle medium and high bandwidth vector and viruses.
- Gear 1: throttle high bandwidth vector and viruses.
- Gear 2: throttle power viruses only.

This ensures these counters are enabled and context-switched as
expected.

Change-Id: I6df6e0fe3a5362861aa967a78ab7c34fc4bb8fc3
Signed-off-by: Chris Kay <chris.kay@arm.com>
This commit is contained in:
Chris Kay 2021-05-18 18:49:51 +01:00
parent 68120783d6
commit c19a82bef0
2 changed files with 46 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
fdts/tc.dts
View File

@ -79,6 +79,31 @@
};
};
amus {
amu: amu-0 {
#address-cells = <1>;
#size-cells = <0>;
mpmm_gear0: counter@0 {
reg = <0>;
enable-at-el3;
};
mpmm_gear1: counter@1 {
reg = <1>;
enable-at-el3;
};
mpmm_gear2: counter@2 {
reg = <2>;
enable-at-el3;
};
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
@ -87,6 +112,8 @@
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
amu = <&amu>;
supports-mpmm;
};
CPU1:cpu@100 {
@ -97,6 +124,8 @@
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
amu = <&amu>;
supports-mpmm;
};
CPU2:cpu@200 {
@ -107,6 +136,8 @@
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
amu = <&amu>;
supports-mpmm;
};
CPU3:cpu@300 {
@ -117,6 +148,8 @@
clocks = <&scmi_dvfs 0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <406>;
amu = <&amu>;
supports-mpmm;
};
CPU4:cpu@400 {
@ -127,6 +160,8 @@
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
amu = <&amu>;
supports-mpmm;
};
CPU5:cpu@500 {
@ -137,6 +172,8 @@
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
amu = <&amu>;
supports-mpmm;
};
CPU6:cpu@600 {
@ -147,6 +184,8 @@
clocks = <&scmi_dvfs 1>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <912>;
amu = <&amu>;
supports-mpmm;
};
CPU7:cpu@700 {
@ -157,6 +196,8 @@
clocks = <&scmi_dvfs 2>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <1024>;
amu = <&amu>;
supports-mpmm;
};
};

5
plat/arm/board/tc/platform.mk
View File

@ -140,6 +140,11 @@ override CTX_INCLUDE_PAUTH_REGS := 1
override ENABLE_SPE_FOR_LOWER_ELS := 0
override ENABLE_AMU := 1
override ENABLE_AMU_AUXILIARY_COUNTERS := 1
override ENABLE_AMU_FCONF := 1
override ENABLE_MPMM := 1
override ENABLE_MPMM_FCONF := 1
include plat/arm/common/arm_common.mk
include plat/arm/css/common/css_common.mk