Add SPI-NAND framework
This framework supports SPI-NAND and is based on the SPI-MEM framework for SPI operations. It uses a common high level access using the io_mtd. It is limited to the read functionalities. Default behavior is the basic one data line operation but it could be overridden by platform. Change-Id: Icb4e0887c4003a826f47c876479dd004a323a32b Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
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Lionel Debieve
parent
05e6a5638b
commit
c3e5773904
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stddef.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/spi_nand.h>
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#include <lib/utils.h>
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#define SPI_NAND_MAX_ID_LEN 4U
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#define DELAY_US_400MS 400000U
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#define MACRONIX_ID 0xC2U
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static struct spinand_device spinand_dev;
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#pragma weak plat_get_spi_nand_data
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int plat_get_spi_nand_data(struct spinand_device *device)
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{
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return 0;
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}
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static int spi_nand_reg(bool read_reg, uint8_t reg, uint8_t *val,
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enum spi_mem_data_dir dir)
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{
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struct spi_mem_op op;
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zeromem(&op, sizeof(struct spi_mem_op));
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if (read_reg) {
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op.cmd.opcode = SPI_NAND_OP_GET_FEATURE;
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} else {
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op.cmd.opcode = SPI_NAND_OP_SET_FEATURE;
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}
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op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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op.addr.val = reg;
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op.addr.nbytes = 1U;
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op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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op.data.dir = dir;
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op.data.nbytes = 1U;
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op.data.buf = val;
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return spi_mem_exec_op(&op);
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}
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static int spi_nand_read_reg(uint8_t reg, uint8_t *val)
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{
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return spi_nand_reg(true, reg, val, SPI_MEM_DATA_IN);
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}
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static int spi_nand_write_reg(uint8_t reg, uint8_t val)
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{
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return spi_nand_reg(false, reg, &val, SPI_MEM_DATA_OUT);
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}
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static int spi_nand_update_cfg(uint8_t mask, uint8_t val)
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{
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int ret;
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uint8_t cfg = spinand_dev.cfg_cache;
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cfg &= ~mask;
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cfg |= val;
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if (cfg == spinand_dev.cfg_cache) {
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return 0;
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}
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ret = spi_nand_write_reg(SPI_NAND_REG_CFG, cfg);
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if (ret == 0) {
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spinand_dev.cfg_cache = cfg;
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}
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return ret;
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}
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static int spi_nand_ecc_enable(bool enable)
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{
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return spi_nand_update_cfg(SPI_NAND_CFG_ECC_EN,
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enable ? SPI_NAND_CFG_ECC_EN : 0U);
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}
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static int spi_nand_quad_enable(uint8_t manufacturer_id)
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{
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bool enable = false;
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if (manufacturer_id != MACRONIX_ID) {
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return 0;
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}
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if (spinand_dev.spi_read_cache_op.data.buswidth ==
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SPI_MEM_BUSWIDTH_4_LINE) {
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enable = true;
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}
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return spi_nand_update_cfg(SPI_NAND_CFG_QE,
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enable ? SPI_NAND_CFG_QE : 0U);
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}
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static int spi_nand_wait_ready(uint8_t *status)
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{
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int ret;
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uint64_t timeout = timeout_init_us(DELAY_US_400MS);
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while (!timeout_elapsed(timeout)) {
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ret = spi_nand_read_reg(SPI_NAND_REG_STATUS, status);
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if (ret != 0) {
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return ret;
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}
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VERBOSE("%s Status %x\n", __func__, *status);
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if ((*status & SPI_NAND_STATUS_BUSY) == 0U) {
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return 0;
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}
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}
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return -ETIMEDOUT;
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}
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static int spi_nand_reset(void)
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{
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struct spi_mem_op op;
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uint8_t status;
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int ret;
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zeromem(&op, sizeof(struct spi_mem_op));
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op.cmd.opcode = SPI_NAND_OP_RESET;
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op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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ret = spi_mem_exec_op(&op);
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if (ret != 0) {
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return ret;
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}
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return spi_nand_wait_ready(&status);
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}
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static int spi_nand_read_id(uint8_t *id)
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{
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struct spi_mem_op op;
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zeromem(&op, sizeof(struct spi_mem_op));
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op.cmd.opcode = SPI_NAND_OP_READ_ID;
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op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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op.data.dir = SPI_MEM_DATA_IN;
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op.data.nbytes = SPI_NAND_MAX_ID_LEN;
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op.data.buf = id;
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op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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return spi_mem_exec_op(&op);
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}
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static int spi_nand_load_page(unsigned int page)
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{
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struct spi_mem_op op;
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uint32_t block_nb = page / spinand_dev.nand_dev->block_size;
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uint32_t page_nb = page - (block_nb * spinand_dev.nand_dev->page_size);
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uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size /
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spinand_dev.nand_dev->page_size;
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uint32_t block_sh = __builtin_ctz(nbpages_per_block) + 1U;
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zeromem(&op, sizeof(struct spi_mem_op));
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op.cmd.opcode = SPI_NAND_OP_LOAD_PAGE;
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op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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op.addr.val = (block_nb << block_sh) | page_nb;
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op.addr.nbytes = 3U;
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op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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return spi_mem_exec_op(&op);
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}
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static int spi_nand_read_from_cache(unsigned int page, unsigned int offset,
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uint8_t *buffer, unsigned int len)
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{
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uint32_t nbpages_per_block = spinand_dev.nand_dev->block_size /
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spinand_dev.nand_dev->page_size;
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uint32_t block_nb = page / nbpages_per_block;
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uint32_t page_sh = __builtin_ctz(spinand_dev.nand_dev->page_size) + 1U;
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spinand_dev.spi_read_cache_op.addr.val = offset;
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if ((spinand_dev.nand_dev->nb_planes > 1U) && ((block_nb % 2U) == 1U)) {
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spinand_dev.spi_read_cache_op.addr.val |= 1U << page_sh;
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}
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spinand_dev.spi_read_cache_op.data.buf = buffer;
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spinand_dev.spi_read_cache_op.data.nbytes = len;
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return spi_mem_exec_op(&spinand_dev.spi_read_cache_op);
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}
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static int spi_nand_read_page(unsigned int page, unsigned int offset,
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uint8_t *buffer, unsigned int len,
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bool ecc_enabled)
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{
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uint8_t status;
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int ret;
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ret = spi_nand_ecc_enable(ecc_enabled);
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if (ret != 0) {
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return ret;
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}
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ret = spi_nand_load_page(page);
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if (ret != 0) {
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return ret;
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}
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ret = spi_nand_wait_ready(&status);
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if (ret != 0) {
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return ret;
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}
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ret = spi_nand_read_from_cache(page, offset, buffer, len);
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if (ret != 0) {
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return ret;
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}
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if (ecc_enabled && ((status & SPI_NAND_STATUS_ECC_UNCOR) != 0U)) {
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return -EBADMSG;
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}
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return 0;
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}
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static int spi_nand_mtd_block_is_bad(unsigned int block)
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{
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unsigned int nbpages_per_block = spinand_dev.nand_dev->block_size /
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spinand_dev.nand_dev->page_size;
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uint8_t bbm_marker[2];
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int ret;
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ret = spi_nand_read_page(block * nbpages_per_block,
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spinand_dev.nand_dev->page_size,
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bbm_marker, sizeof(bbm_marker), false);
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if (ret != 0) {
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return ret;
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}
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if ((bbm_marker[0] != GENMASK_32(7, 0)) ||
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(bbm_marker[1] != GENMASK_32(7, 0))) {
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WARN("Block %i is bad\n", block);
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return 1;
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}
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return 0;
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}
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static int spi_nand_mtd_read_page(struct nand_device *nand, unsigned int page,
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uintptr_t buffer)
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{
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return spi_nand_read_page(page, 0, (uint8_t *)buffer,
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spinand_dev.nand_dev->page_size, true);
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}
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int spi_nand_init(unsigned long long *size, unsigned int *erase_size)
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{
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uint8_t id[SPI_NAND_MAX_ID_LEN];
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int ret;
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spinand_dev.nand_dev = get_nand_device();
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if (spinand_dev.nand_dev == NULL) {
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return -EINVAL;
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}
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spinand_dev.nand_dev->mtd_block_is_bad = spi_nand_mtd_block_is_bad;
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spinand_dev.nand_dev->mtd_read_page = spi_nand_mtd_read_page;
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spinand_dev.nand_dev->nb_planes = 1;
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spinand_dev.spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE;
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spinand_dev.spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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spinand_dev.spi_read_cache_op.addr.nbytes = 2U;
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spinand_dev.spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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spinand_dev.spi_read_cache_op.dummy.nbytes = 1U;
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spinand_dev.spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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spinand_dev.spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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if (plat_get_spi_nand_data(&spinand_dev) != 0) {
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return -EINVAL;
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}
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ret = spi_nand_reset();
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if (ret != 0) {
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return ret;
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}
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ret = spi_nand_read_id(id);
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if (ret != 0) {
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return ret;
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}
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ret = spi_nand_read_reg(SPI_NAND_REG_CFG, &spinand_dev.cfg_cache);
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if (ret != 0) {
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return ret;
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}
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ret = spi_nand_quad_enable(id[0]);
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if (ret != 0) {
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return ret;
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}
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VERBOSE("SPI_NAND Detected ID 0x%x 0x%x\n", id[0], id[1]);
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VERBOSE("Page size %i, Block size %i, size %lli\n",
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spinand_dev.nand_dev->page_size,
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spinand_dev.nand_dev->block_size,
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spinand_dev.nand_dev->size);
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*size = spinand_dev.nand_dev->size;
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*erase_size = spinand_dev.nand_dev->block_size;
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return 0;
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}
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@ -0,0 +1,49 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRIVERS_SPI_NAND_H
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#define DRIVERS_SPI_NAND_H
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#include <drivers/nand.h>
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#include <drivers/spi_mem.h>
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#define SPI_NAND_OP_GET_FEATURE 0x0FU
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#define SPI_NAND_OP_SET_FEATURE 0x1FU
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#define SPI_NAND_OP_READ_ID 0x9FU
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#define SPI_NAND_OP_LOAD_PAGE 0x13U
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#define SPI_NAND_OP_RESET 0xFFU
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#define SPI_NAND_OP_READ_FROM_CACHE 0x03U
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#define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU
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#define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU
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/* Configuration register */
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#define SPI_NAND_REG_CFG 0xB0U
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#define SPI_NAND_CFG_ECC_EN BIT(4)
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#define SPI_NAND_CFG_QE BIT(0)
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/* Status register */
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#define SPI_NAND_REG_STATUS 0xC0U
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#define SPI_NAND_STATUS_BUSY BIT(0)
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#define SPI_NAND_STATUS_ECC_UNCOR BIT(5)
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struct spinand_device {
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struct nand_device *nand_dev;
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struct spi_mem_op spi_read_cache_op;
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uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */
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};
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int spi_nand_init(unsigned long long *size, unsigned int *erase_size);
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/*
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* Platform can implement this to override default SPI-NAND instance
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* configuration.
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*
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* @device: target SPI-NAND instance.
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* Return 0 on success, negative value otherwise.
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*/
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int plat_get_spi_nand_data(struct spinand_device *device);
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#endif /* DRIVERS_SPI_NAND_H */
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