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Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatch 

Clarify comments in xlat tables lib and fixes related to the TLB
This commit is contained in:
davidcunado-arm 2018-02-28 01:26:21 +00:00 committed by GitHub
parent 99e198ecd8 2644103063
commit c69145fc2a
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GPG Key ID: 4AEE18F83AFDEB23
13 changed files with 113 additions and 34 deletions
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5
bl1/bl1.ld.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -129,7 +129,8 @@ SECTIONS
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unecessary zero init
* the .bss section. The tables are initialized to zero by the translation
* tables library.
*/
xlat_table (NOLOAD) : {
*(xlat_table)

5
bl2/bl2.ld.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -108,7 +108,8 @@ SECTIONS
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unecessary zero init
* the .bss section. The tables are initialized to zero by the translation
* tables library.
*/
xlat_table (NOLOAD) : {
*(xlat_table)

5
bl2/bl2_el3.ld.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -139,7 +139,8 @@ SECTIONS
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unnecessary zero init
* the .bss section. The tables are initialized to zero by the translation
* tables library.
*/
xlat_table (NOLOAD) : {
*(xlat_table)

5
bl2u/bl2u.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -95,7 +95,8 @@ SECTIONS
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unecessary zero init
* the .bss section. The tables are initialized to zero by the translation
* tables library.
*/
xlat_table (NOLOAD) : {
*(xlat_table)

2
bl31/aarch64/bl31_entrypoint.S
View File

@ -9,7 +9,7 @@
#include <el3_common_macros.S>
#include <pmf_asm_macros.S>
#include <runtime_instr.h>
#include <xlat_tables_defs.h>
#include <xlat_mmu_helpers.h>
.globl bl31_entrypoint
.globl bl31_warm_entrypoint

5
bl31/bl31.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -217,7 +217,8 @@ SECTIONS
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unecessary zero init
* the .bss section. The tables are initialized to zero by the translation
* tables library.
*/
xlat_table (NOLOAD) : {
#if ENABLE_SPM

5
bl32/sp_min/sp_min.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -176,7 +176,8 @@ SECTIONS
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unecessary zero init
* the .bss section. The tables are initialized to zero by the translation
* tables library.
*/
xlat_table (NOLOAD) : {
*(xlat_table)

5
bl32/tsp/tsp.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -94,7 +94,8 @@ SECTIONS
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unecessary zero init
* the .bss section. The tables are initialized to zero by the translation
* tables library.
*/
xlat_table (NOLOAD) : {
*(xlat_table)

42
include/lib/xlat_tables/xlat_mmu_helpers.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,13 +7,51 @@
#ifndef __XLAT_MMU_HELPERS_H__
#define __XLAT_MMU_HELPERS_H__
/*
* The following flags are passed to enable_mmu_xxx() to override the default
* values used to program system registers while enabling the MMU.
*/
/*
* When this flag is used, all data access to Normal memory from this EL and all
* Normal memory accesses to the translation tables of this EL are non-cacheable
* for all levels of data and unified cache until the caches are enabled by
* setting the bit SCTLR_ELx.C.
*/
#define DISABLE_DCACHE (U(1) << 0)
/*
* Mark the translation tables as non-cacheable for the MMU table walker, which
* is a different observer from the PE/CPU. If the flag is not specified, the
* tables are cacheable for the MMU table walker.
*
* Note that, as far as the PE/CPU observer is concerned, the attributes used
* are the ones specified in the translation tables themselves. The MAIR
* register specifies the cacheability through the field AttrIndx of the lower
* attributes of the translation tables. The shareability is specified in the SH
* field of the lower attributes.
*
* The MMU table walker uses the attributes specified in the fields ORGNn, IRGNn
* and SHn of the TCR register to access the translation tables.
*
* The attributes specified in the TCR register and the tables can be different
* as there are no checks to prevent that. Special care must be taken to ensure
* that there aren't mismatches. The behaviour in that case is described in the
* sections 'Mismatched memory attributes' in the ARMv8 ARM.
*/
#define XLAT_TABLE_NC (U(1) << 1)
#ifndef __ASSEMBLY__
#ifdef AARCH32
/* AArch32 specific translation table API */
void enable_mmu_secure(uint32_t flags);
void enable_mmu_secure(unsigned int flags);
#else
/* AArch64 specific translation table APIs */
void enable_mmu_el1(unsigned int flags);
void enable_mmu_el3(unsigned int flags);
#endif /* AARCH32 */
#endif /* __ASSEMBLY__ */
#endif /* __XLAT_MMU_HELPERS_H__ */

15
include/lib/xlat_tables/xlat_tables_defs.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,6 +9,7 @@
#include <arch.h>
#include <utils_def.h>
#include <xlat_mmu_helpers.h>
/* Miscellaneous MMU related constants */
#define NUM_2MB_IN_GB (U(1) << 9)
@ -165,16 +166,4 @@
#define XN_SHIFT 54
#define UXN_SHIFT XN_SHIFT
/*
* Flags to override default values used to program system registers while
* enabling the MMU.
*/
#define DISABLE_DCACHE (U(1) << 0)
/*
* This flag marks the translation tables are Non-cacheable for MMU accesses.
* If the flag is not specified, by default the tables are cacheable.
*/
#define XLAT_TABLE_NC (U(1) << 1)
#endif /* __XLAT_TABLES_DEFS_H__ */

24
lib/psci/aarch32/psci_helpers.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -91,6 +91,28 @@ func psci_do_pwrup_cache_maintenance
stcopr r0, SCTLR
isb
#if PLAT_XLAT_TABLES_DYNAMIC
/* ---------------------------------------------
* During warm boot the MMU is enabled with data
* cache disabled, then the interconnect is set
* up and finally the data cache is enabled.
*
* During this period, if another CPU modifies
* the translation tables, the MMU table walker
* may read the old entries. This is only a
* problem for dynamic regions, the warm boot
* code isn't affected because it is static.
*
* Invalidate all TLB entries loaded while the
* CPU wasn't coherent with the rest of the
* system.
* ---------------------------------------------
*/
stcopr r0, TLBIALL
dsb ish
isb
#endif
pop {r12, pc}
endfunc psci_do_pwrup_cache_maintenance

24
lib/psci/aarch64/psci_helpers.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -115,6 +115,28 @@ func psci_do_pwrup_cache_maintenance
msr sctlr_el3, x0
isb
#if PLAT_XLAT_TABLES_DYNAMIC
/* ---------------------------------------------
* During warm boot the MMU is enabled with data
* cache disabled, then the interconnect is set
* up and finally the data cache is enabled.
*
* During this period, if another CPU modifies
* the translation tables, the MMU table walker
* may read the old entries. This is only a
* problem for dynamic regions, the warm boot
* code isn't affected because it is static.
*
* Invalidate all TLB entries loaded while the
* CPU wasn't coherent with the rest of the
* system.
* ---------------------------------------------
*/
tlbi alle3
dsb ish
isb
#endif
ldp x29, x30, [sp], #16
ret
endfunc psci_do_pwrup_cache_maintenance

5
plat/mediatek/mt6795/bl31.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -132,7 +132,8 @@ SECTIONS
/*
* The xlat_table section is for full, aligned page tables (4K).
* Removing them from .bss avoids forcing 4K alignment on
* the .bss section and eliminates the unecessary zero init
* the .bss section. The tables are initialized to zero by the translation
* tables library.
*/
xlat_table (NOLOAD) : {
*(xlat_table)