Corstone700: add support for mhuv2 in arm TF-A
Note: This patch implements in-band messaging protocol only. ARM has launched a next version of MHU i.e. MHUv2 with its latest subsystems. The main change is that the MHUv2 is now a distributed IP with different peripheral views (registers) for the sender and receiver. Another main difference is that MHUv1 duplex channels are now split into simplex/half duplex in MHUv2. MHUv2 has a configurable number of communication channels. There is a capability register (MSG_NO_CAP) to find out how many channels are available in a system. The register offsets have also changed for STAT, SET & CLEAR registers from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively. 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | | SET | | | ------------------------....----- Transmit Channel 0x0 0x4 0x8 0xC 0x1F ------------------------....----- | STAT | | CLR | | | | ------------------------....----- Receive Channel The MHU controller can request the receiver to wake-up and once the request is removed, the receiver may go back to sleep, but the MHU itself does not actively put a receiver to sleep. So, in order to wake-up the receiver when the sender wants to send data, the sender has to set ACCESS_REQUEST register first in order to wake-up receiver, state of which can be detected using ACCESS_READY register. ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset of 0xF8C and are accessible only on any sender channel. This patch adds necessary changes in a new file required to support the latest MHUv2 controller. This patch also needs an update in DT binding for ARM MHUv2 as we need a second register base (tx base) which would be used as the send channel base. Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6 Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
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@ -1,10 +1,12 @@
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/*
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* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <mhu.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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@ -26,6 +28,7 @@ const mmap_region_t plat_arm_mmap[] = {
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*/
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void __init plat_arm_pwrc_setup(void)
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{
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mhu_secure_init();
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}
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unsigned int plat_get_syscnt_freq2(void)
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@ -0,0 +1,117 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include "mhu.h"
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#include <plat_arm.h>
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#include <platform_def.h>
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ARM_INSTANTIATE_LOCK;
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#pragma weak plat_arm_pwrc_setup
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/*
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* Slot 31 is reserved because the MHU hardware uses this register bit to
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* indicate a non-secure access attempt. The total number of available slots is
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* therefore 31 [30:0].
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*/
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#define MHU_MAX_SLOT_ID 30
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void mhu_secure_message_start(uintptr_t address, unsigned int slot_id)
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{
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unsigned int intr_stat_check;
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uint64_t timeout_cnt;
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volatile uint8_t expiration;
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assert(slot_id <= MHU_MAX_SLOT_ID);
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arm_lock_get();
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/*
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* Make sure any previous command has finished
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* and polling timeout not expired
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*/
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timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT);
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do {
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intr_stat_check = (mmio_read_32(address + CPU_INTR_S_STAT) &
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(1 << slot_id));
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expiration = timeout_elapsed(timeout_cnt);
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} while ((intr_stat_check != 0U) && (expiration == 0U));
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/*
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* Note: No risk of timer overflows while waiting
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* for the timeout expiration.
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* According to Armv8 TRM: System counter roll-over
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* time of not less than 40 years
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*/
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}
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void mhu_secure_message_send(uintptr_t address,
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unsigned int slot_id,
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unsigned int message)
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{
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unsigned char access_ready;
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uint64_t timeout_cnt;
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volatile uint8_t expiration;
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assert(slot_id <= MHU_MAX_SLOT_ID);
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assert((mmio_read_32(address + CPU_INTR_S_STAT) &
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(1 << slot_id)) == 0U);
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MHU_V2_ACCESS_REQUEST(address);
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timeout_cnt = timeout_init_us(MHU_POLL_INTR_STAT_TIMEOUT);
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do {
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access_ready = MHU_V2_IS_ACCESS_READY(address);
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expiration = timeout_elapsed(timeout_cnt);
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} while ((access_ready == 0U) && (expiration == 0U));
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/*
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* Note: No risk of timer overflows while waiting
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* for the timeout expiration.
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* According to Armv8 TRM: System counter roll-over
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* time of not less than 40 years
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*/
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mmio_write_32(address + CPU_INTR_S_SET, message);
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}
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void mhu_secure_message_end(uintptr_t address, unsigned int slot_id)
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{
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assert(slot_id <= MHU_MAX_SLOT_ID);
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/*
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* Clear any response we got by writing one in the relevant slot bit to
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* the CLEAR register
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*/
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MHU_V2_CLEAR_REQUEST(address);
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arm_lock_release();
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}
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void __init mhu_secure_init(void)
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{
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arm_lock_init();
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/*
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* The STAT register resets to zero. Ensure it is in the expected state,
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* as a stale or garbage value would make us think it's a message we've
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* already sent.
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*/
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assert(mmio_read_32(PLAT_SDK700_MHU0_SEND + CPU_INTR_S_STAT) == 0);
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}
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@ -0,0 +1,37 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MHU_H
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#define MHU_H
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#define MHU_POLL_INTR_STAT_TIMEOUT 50000 /*timeout value in us*/
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/* CPU MHU secure channel registers */
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#define CPU_INTR_S_STAT 0x00
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#define CPU_INTR_S_SET 0x0C
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/* MHUv2 Control Registers Offsets */
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#define MHU_V2_MSG_CFG_OFFSET 0xF80
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#define MHU_V2_ACCESS_REQ_OFFSET 0xF88
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#define MHU_V2_ACCESS_READY_OFFSET 0xF8C
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#define MHU_V2_ACCESS_REQUEST(addr) \
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mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1)
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#define MHU_V2_CLEAR_REQUEST(addr) \
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mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0)
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#define MHU_V2_IS_ACCESS_READY(addr) \
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(mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1)
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void mhu_secure_message_start(uintptr_t address, unsigned int slot_id);
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void mhu_secure_message_send(uintptr_t address,
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unsigned int slot_id,
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unsigned int message);
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void mhu_secure_message_end(uintptr_t address, unsigned int slot_id);
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void mhu_secure_init(void);
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#endif /* MHU_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define PLAT_ARM_GICD_BASE 0x1C010000
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#define PLAT_ARM_GICC_BASE 0x1C02F000
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/* MHUv2 Secure Channel receiver and sender */
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#define PLAT_SDK700_MHU0_SEND 0x1B800000
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#define PLAT_SDK700_MHU0_RECV 0x1B810000
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/* Timer/watchdog related constants */
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#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
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#define ARM_SYS_CNTREAD_BASE UL(0x1a210000)
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#
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# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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plat/arm/common/arm_common.c \
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lib/xlat_tables/aarch32/xlat_tables.c \
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lib/xlat_tables/xlat_tables_common.c \
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${CORSTONE700_CPU_LIBS}
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${CORSTONE700_CPU_LIBS} \
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plat/arm/board/corstone700/drivers/mhu/mhu.c
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PLAT_INCLUDES := -Iplat/arm/board/corstone700/include
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PLAT_INCLUDES := -Iplat/arm/board/corstone700/include \
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-Iinclude/plat/arm/common \
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-Iplat/arm/board/corstone700/drivers/mhu
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NEED_BL32 := yes
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CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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plat/common/plat_gicv2.c \
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CORSTONE700_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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plat/common/plat_gicv2.c \
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plat/arm/common/arm_gicv2.c
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# BL1/BL2 Image not a part of the capsule Image for Corstone700
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