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intel: Refactor common platform code [4/5] 

Pull out SiP & PSCI service driver into socfpga common directory.
Remove deassert_peripheral_reset from cold reset procedure as it is not
needed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd
This commit is contained in:
Hadi Asyrafi 2019-10-23 17:35:32 +08:00
parent d09adcbaf2
commit c76d423989
4 changed files with 12 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
plat/intel/soc/agilex/platform.mk
View File

@ -57,9 +57,9 @@ BL31_SOURCES += \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/aem_generic.S \
plat/common/plat_psci_common.c \
plat/intel/soc/agilex/socfpga_sip_svc.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/agilex/bl31_plat_setup.c \
plat/intel/soc/agilex/socfpga_psci.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \

20
plat/intel/soc/agilex/socfpga_psci.c → plat/intel/soc/common/socfpga_psci.c
View File

@ -11,13 +11,11 @@
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
#include "agilex_reset_manager.h"
#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"
#define AGX_RSTMGR_OFST 0xffd11000
#define AGX_RSTMGR_MPUMODRST_OFST 0x20
uintptr_t *agilex_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
/*******************************************************************************
@ -50,8 +48,7 @@ int socfpga_pwr_domain_on(u_register_t mpidr)
*cpuid_release = cpu_id;
/* release core reset */
mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
1 << cpu_id);
mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
return PSCI_E_SUCCESS;
}
@ -81,8 +78,7 @@ void socfpga_pwr_domain_suspend(const psci_power_state_t *target_state)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
/* assert core reset */
mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
1 << cpu_id);
mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
}
@ -121,8 +117,7 @@ void socfpga_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
__func__, i, target_state->pwr_domain_state[i]);
/* release core reset */
mmio_clrbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
1 << cpu_id);
mmio_clrbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
}
/*******************************************************************************
@ -137,9 +132,6 @@ static void __dead2 socfpga_system_off(void)
static void __dead2 socfpga_system_reset(void)
{
INFO("assert Peripheral from Reset\r\n");
deassert_peripheral_reset();
mailbox_reset_cold();
while (1)
@ -191,7 +183,7 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const struct plat_psci_ops **psci_ops)
{
/* Save warm boot entrypoint.*/
*agilex_sec_entry = sec_entrypoint;
*socfpga_sec_entry = sec_entrypoint;
*psci_ops = &socfpga_psci_pm_ops;
return 0;

4
plat/intel/soc/agilex/socfpga_sip_svc.c → plat/intel/soc/common/socfpga_sip_svc.c
View File

@ -360,7 +360,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
}
DECLARE_RT_SVC(
agilex_sip_svc,
socfpga_sip_svc,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
@ -369,7 +369,7 @@ DECLARE_RT_SVC(
);
DECLARE_RT_SVC(
agilex_sip_svc_std,
socfpga_sip_svc_std,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_YIELD,

4
plat/intel/soc/stratix10/platform.mk
View File

@ -55,9 +55,9 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
plat/intel/soc/stratix10/plat_sip_svc.c \
plat/intel/soc/common/socfpga_sip_svc.c \
plat/intel/soc/stratix10/bl31_plat_setup.c \
plat/intel/soc/stratix10/plat_psci.c \
plat/intel/soc/common/socfpga_psci.c \
plat/intel/soc/common/socfpga_topology.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c\