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Merge changes from topic "imx8mp-tbbr" into integration 

* changes:
  feat(plat/imx/imx8m/imx8mp): enable Trusted Boot
  feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP
  refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common
  feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout
  refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common
  feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build
This commit is contained in:
Manish Pandey 2021-10-04 12:47:07 +02:00 committed by TrustedFirmware Code Review
parent 6acaba6238 a16ecd2cff
commit caf8fdb712
19 changed files with 425 additions and 303 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
plat/imx/imx8m/imx8mm/imx8mm_io_storage.c → plat/imx/common/imx_io_storage.c
View File

@ -6,10 +6,10 @@
#include <assert.h>
#include <common/debug.h>
#include <drivers/io/io_block.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_fip.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_memmap.h>
#include <drivers/mmc.h>
#include <lib/utils_def.h>
@ -21,21 +21,21 @@
static const io_dev_connector_t *fip_dev_con;
static uintptr_t fip_dev_handle;
#ifndef IMX8MM_FIP_MMAP
#ifndef IMX_FIP_MMAP
static const io_dev_connector_t *mmc_dev_con;
static uintptr_t mmc_dev_handle;
static const io_block_spec_t mmc_fip_spec = {
.offset = IMX8MM_FIP_MMC_BASE,
.length = IMX8MM_FIP_SIZE
.offset = IMX_FIP_MMC_BASE,
.length = IMX_FIP_SIZE
};
static const io_block_dev_spec_t mmc_dev_spec = {
/* It's used as temp buffer in block driver. */
.buffer = {
.offset = IMX8MM_FIP_BASE,
.offset = IMX_FIP_BASE,
/* do we need a new value? */
.length = IMX8MM_FIP_SIZE
.length = IMX_FIP_SIZE
},
.ops = {
.read = mmc_read_blocks,
@ -51,8 +51,8 @@ static const io_dev_connector_t *memmap_dev_con;
static uintptr_t memmap_dev_handle;
static const io_block_spec_t fip_block_spec = {
.offset = IMX8MM_FIP_BASE,
.length = IMX8MM_FIP_SIZE
.offset = IMX_FIP_BASE,
.length = IMX_FIP_SIZE
};
static int open_memmap(const uintptr_t spec);
#endif
@ -113,6 +113,7 @@ static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
};
#endif /* TRUSTED_BOARD_BOOT */
/* TODO: this structure is replicated multiple times. rationalize it ! */
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
@ -120,7 +121,7 @@ struct plat_io_policy {
};
static const struct plat_io_policy policies[] = {
#ifndef IMX8MM_FIP_MMAP
#ifndef IMX_FIP_MMAP
[FIP_IMAGE_ID] = {
&mmc_dev_handle,
(uintptr_t)&mmc_fip_spec,
@ -219,7 +220,7 @@ static int open_fip(const uintptr_t spec)
return result;
}
#ifndef IMX8MM_FIP_MMAP
#ifndef IMX_FIP_MMAP
static int open_mmc(const uintptr_t spec)
{
int result;
@ -270,11 +271,11 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
return result;
}
void plat_imx8mm_io_setup(void)
void plat_imx_io_setup(void)
{
int result __unused;
#ifndef IMX8MM_FIP_MMAP
#ifndef IMX_FIP_MMAP
result = register_io_dev_block(&mmc_dev_con);
assert(result == 0);

3
plat/imx/imx7/common/imx7.mk
View File

@ -16,6 +16,7 @@ PLAT_INCLUDES := -Idrivers/imx/uart \
-Iplat/imx/imx7/include \
-Idrivers/imx/timer \
-Idrivers/imx/usdhc \
-Iinclude/common/tbbr
# Translation tables library
include lib/xlat_tables_v2/xlat_tables.mk
@ -46,7 +47,7 @@ BL2_SOURCES += common/desc_image_load.c \
plat/imx/imx7/common/imx7_bl2_el3_common.c \
plat/imx/imx7/common/imx7_helpers.S \
plat/imx/imx7/common/imx7_image_load.c \
plat/imx/imx7/common/imx7_io_storage.c \
plat/imx/common/imx_io_storage.c \
plat/imx/common/aarch32/imx_uart_console.S \
${XLAT_TABLES_LIB_SRCS}

4
plat/imx/imx7/common/imx7_bl2_el3_common.c
View File

@ -173,7 +173,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
console_set_scope(&console, console_scope);
/* Open handles to persistent storage */
plat_imx7_io_setup();
plat_imx_io_setup();
/* Setup higher-level functionality CAAM, RTC etc */
imx_caam_init();
@ -183,7 +183,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
VERBOSE("\tOPTEE 0x%08x-0x%08x\n", IMX7_OPTEE_BASE, IMX7_OPTEE_LIMIT);
VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
VERBOSE("\tFIP 0x%08x-0x%08x\n", IMX7_FIP_BASE, IMX7_FIP_LIMIT);
VERBOSE("\tFIP 0x%08x-0x%08x\n", IMX_FIP_BASE, IMX_FIP_LIMIT);
VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", IMX7_DTB_OVERLAY_BASE, IMX7_DTB_OVERLAY_LIMIT);
VERBOSE("\tDTB 0x%08x-0x%08x\n", IMX7_DTB_BASE, IMX7_DTB_LIMIT);
VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", IMX7_UBOOT_BASE, IMX7_UBOOT_LIMIT);

270
plat/imx/imx7/common/imx7_io_storage.c
View File

@ -1,270 +0,0 @@
/*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/io/io_block.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_fip.h>
#include <drivers/io/io_memmap.h>
#include <drivers/mmc.h>
#include <tools_share/firmware_image_package.h>
static const io_dev_connector_t *fip_dev_con;
static uintptr_t fip_dev_handle;
#ifndef IMX7_FIP_MMAP
static const io_dev_connector_t *mmc_dev_con;
static uintptr_t mmc_dev_handle;
static const io_block_spec_t mmc_fip_spec = {
.offset = IMX7_FIP_MMC_BASE,
.length = IMX7_FIP_SIZE
};
static const io_block_dev_spec_t mmc_dev_spec = {
/* It's used as temp buffer in block driver. */
.buffer = {
.offset = IMX7_FIP_BASE,
/* do we need a new value? */
.length = IMX7_FIP_SIZE
},
.ops = {
.read = mmc_read_blocks,
.write = mmc_write_blocks,
},
.block_size = MMC_BLOCK_SIZE,
};
static int open_mmc(const uintptr_t spec);
#else
static const io_dev_connector_t *memmap_dev_con;
static uintptr_t memmap_dev_handle;
static const io_block_spec_t fip_block_spec = {
.offset = IMX7_FIP_BASE,
.length = IMX7_FIP_SIZE
};
static int open_memmap(const uintptr_t spec);
#endif
static int open_fip(const uintptr_t spec);
static const io_uuid_spec_t bl32_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32,
};
static const io_uuid_spec_t bl32_extra1_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
};
static const io_uuid_spec_t bl32_extra2_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
};
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
#if TRUSTED_BOARD_BOOT
static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
.uuid = UUID_TRUSTED_BOOT_FW_CERT,
};
static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
.uuid = UUID_TRUSTED_KEY_CERT,
};
static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
.uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
};
static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
.uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
};
static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
};
static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
};
#endif /* TRUSTED_BOARD_BOOT */
/* TODO: this structure is replicated multiple times. rationalize it ! */
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
#ifndef IMX7_FIP_MMAP
[FIP_IMAGE_ID] = {
&mmc_dev_handle,
(uintptr_t)&mmc_fip_spec,
open_mmc
},
#else
[FIP_IMAGE_ID] = {
&memmap_dev_handle,
(uintptr_t)&fip_block_spec,
open_memmap
},
#endif
[BL32_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_uuid_spec,
open_fip
},
[BL32_EXTRA1_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_extra1_uuid_spec,
open_fip
},
[BL32_EXTRA2_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_extra2_uuid_spec,
open_fip
},
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,
open_fip
},
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&tb_fw_cert_uuid_spec,
open_fip
},
[TRUSTED_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&trusted_key_cert_uuid_spec,
open_fip
},
[TRUSTED_OS_FW_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&tos_fw_key_cert_uuid_spec,
open_fip
},
[NON_TRUSTED_FW_KEY_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&nt_fw_key_cert_uuid_spec,
open_fip
},
[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&tos_fw_cert_uuid_spec,
open_fip
},
[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&nt_fw_cert_uuid_spec,
open_fip
},
#endif /* TRUSTED_BOARD_BOOT */
};
static int open_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
/* See if a Firmware Image Package is available */
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
if (result == 0) {
result = io_open(fip_dev_handle, spec, &local_image_handle);
if (result == 0) {
VERBOSE("Using FIP\n");
io_close(local_image_handle);
}
}
return result;
}
#ifndef IMX7_FIP_MMAP
static int open_mmc(const uintptr_t spec)
{
int result;
uintptr_t local_handle;
result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
if (result == 0) {
result = io_open(mmc_dev_handle, spec, &local_handle);
if (result == 0)
io_close(local_handle);
}
return result;
}
#else
static int open_memmap(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
if (result == 0) {
result = io_open(memmap_dev_handle, spec, &local_image_handle);
if (result == 0) {
VERBOSE("Using Memmap\n");
io_close(local_image_handle);
}
}
return result;
}
#endif
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
int result;
const struct plat_io_policy *policy;
assert(image_id < ARRAY_SIZE(policies));
policy = &policies[image_id];
result = policy->check(policy->image_spec);
assert(result == 0);
*image_spec = policy->image_spec;
*dev_handle = *policy->dev_handle;
return result;
}
void plat_imx7_io_setup(void)
{
int result __unused;
#ifndef IMX7_FIP_MMAP
result = register_io_dev_block(&mmc_dev_con);
assert(result == 0);
result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
&mmc_dev_handle);
assert(result == 0);
#else
result = register_io_dev_memmap(&memmap_dev_con);
assert(result == 0);
result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
&memmap_dev_handle);
assert(result == 0);
#endif
result = register_io_dev_fip(&fip_dev_con);
assert(result == 0);
result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
&fip_dev_handle);
assert(result == 0);
}

2
plat/imx/imx7/include/imx7_def.h
View File

@ -13,7 +13,7 @@
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void plat_imx7_io_setup(void);
void plat_imx_io_setup(void);
void imx7_platform_setup(u_register_t arg1, u_register_t arg2,
u_register_t arg3, u_register_t arg4);

8
plat/imx/imx7/picopi/include/platform_def.h
View File

@ -92,12 +92,12 @@
#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
/* Define FIP image absolute location 0x80000000 - 0x80100000 */
#define IMX7_FIP_SIZE 0x00100000
#define IMX7_FIP_BASE (DRAM_BASE)
#define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE)
#define IMX_FIP_SIZE 0x00100000
#define IMX_FIP_BASE (DRAM_BASE)
#define IMX_FIP_LIMIT (IMX_FIP_BASE + IMX_FIP_SIZE)
/* Define FIP image location at 1MB offset */
#define IMX7_FIP_MMC_BASE (1024 * 1024)
#define IMX_FIP_MMC_BASE (1024 * 1024)
/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
#define IMX7_DTB_SIZE 0x00100000

8
plat/imx/imx7/warp7/include/platform_def.h
View File

@ -94,12 +94,12 @@
#define IMX7_UBOOT_LIMIT (IMX7_UBOOT_BASE + IMX7_UBOOT_SIZE)
/* Define FIP image absolute location 0x80000000 - 0x80100000 */
#define IMX7_FIP_SIZE 0x00100000
#define IMX7_FIP_BASE (DRAM_BASE)
#define IMX7_FIP_LIMIT (IMX7_FIP_BASE + IMX7_FIP_SIZE)
#define IMX_FIP_SIZE 0x00100000
#define IMX_FIP_BASE (DRAM_BASE)
#define IMX_FIP_LIMIT (IMX_FIP_BASE + IMX_FIP_SIZE)
/* Define FIP image location at 1MB offset */
#define IMX7_FIP_MMC_BASE (1024 * 1024)
#define IMX_FIP_MMC_BASE (1024 * 1024)
/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
#define IMX7_DTB_SIZE 0x00100000

0
plat/imx/imx8m/imx8mm/imx8mm_image_load.c → plat/imx/imx8m/imx8m_image_load.c
View File

2
plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
View File

@ -88,7 +88,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
imx8mm_usdhc_setup();
/* Open handles to a FIP image */
plat_imx8mm_io_setup();
plat_imx_io_setup();
}
void bl2_el3_plat_arch_setup(void)

2
plat/imx/imx8m/imx8mm/include/imx8mm_private.h
View File

@ -10,6 +10,6 @@
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void plat_imx8mm_io_setup(void);
void plat_imx_io_setup(void);
#endif /* IMX8MM_PRIVATE_H */

8
plat/imx/imx8m/imx8mm/include/platform_def.h
View File

@ -41,12 +41,12 @@
#define BL2_LIMIT U(0x940000)
#define BL31_BASE U(0x900000)
#define BL31_LIMIT U(0x920000)
#define IMX8MM_FIP_BASE U(0x40310000)
#define IMX8MM_FIP_SIZE U(0x000300000)
#define IMX8MM_FIP_LIMIT U(FIP_BASE + FIP_SIZE)
#define IMX_FIP_BASE U(0x40310000)
#define IMX_FIP_SIZE U(0x000300000)
#define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE)
/* Define FIP image location on eMMC */
#define IMX8MM_FIP_MMC_BASE U(0x100000)
#define IMX_FIP_MMC_BASE U(0x100000)
#define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */
#else

4
plat/imx/imx8m/imx8mm/platform.mk
View File

@ -63,8 +63,8 @@ BL2_SOURCES += common/desc_image_load.c \
drivers/io/io_storage.c \
drivers/imx/usdhc/imx_usdhc.c \
plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c \
plat/imx/imx8m/imx8mm/imx8mm_io_storage.c \
plat/imx/imx8m/imx8mm/imx8mm_image_load.c \
plat/imx/common/imx_io_storage.c \
plat/imx/imx8m/imx8m_image_load.c \
lib/optee/optee_utils.c
endif

117
plat/imx/imx8m/imx8mp/imx8mp_bl2_el3_setup.c Normal file
View File

@ -0,0 +1,117 @@
/*
* Copyright 2021 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <stdbool.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <common/tbbr/tbbr_img_def.h>
#include <context.h>
#include <drivers/arm/tzc380.h>
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/mmc.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/mmio.h>
#include <lib/optee_utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <imx8m_caam.h>
#include "imx8mp_private.h"
#include <imx_aipstz.h>
#include <imx_rdc.h>
#include <imx_uart.h>
#include <plat/common/platform.h>
#include <plat_imx8.h>
#include <platform_def.h>
static const struct aipstz_cfg aipstz[] = {
{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
{0},
};
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
static console_t console;
unsigned int i;
/* Enable CSU NS access permission */
for (i = 0U; i < 64; i++) {
mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
}
imx_aipstz_init(aipstz);
console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE, &console);
generic_delay_timer_init();
/* select the CKIL source to 32K OSC */
mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
/* Open handles to a FIP image */
plat_imx_io_setup();
}
void bl2_el3_plat_arch_setup(void)
{
}
void bl2_platform_setup(void)
{
}
int bl2_plat_handle_post_image_load(unsigned int image_id)
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
bl_mem_params_node_t *pager_mem_params = NULL;
bl_mem_params_node_t *paged_mem_params = NULL;
assert(bl_mem_params);
switch (image_id) {
case BL32_IMAGE_ID:
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
assert(pager_mem_params);
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
assert(paged_mem_params);
err = parse_optee_header(&bl_mem_params->ep_info,
&pager_mem_params->image_info,
&paged_mem_params->image_info);
if (err != 0) {
WARN("OPTEE header parse error.\n");
}
break;
default:
/* Do nothing in default case */
break;
}
return err;
}
unsigned int plat_get_syscnt_freq2(void)
{
return COUNTER_FREQUENCY;
}
void bl2_plat_runtime_setup(void)
{
return;
}

94
plat/imx/imx8m/imx8mp/imx8mp_bl2_mem_params_desc.c Normal file
View File

@ -0,0 +1,94 @@
/*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
#include <platform_def.h>
static bl_mem_params_node_t bl2_mem_params_descs[] = {
{
.image_id = BL31_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
entry_point_info_t,
SECURE | EXECUTABLE | EP_FIRST_EXE),
.ep_info.pc = BL31_BASE,
.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
IMAGE_ATTRIB_PLAT_SETUP),
.image_info.image_base = BL31_BASE,
.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
{
.image_id = BL32_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
entry_point_info_t,
SECURE | EXECUTABLE),
.ep_info.pc = BL32_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
image_info_t, 0),
.image_info.image_base = BL32_BASE,
.image_info.image_max_size = BL32_SIZE,
.next_handoff_image_id = BL33_IMAGE_ID,
},
{
.image_id = BL32_EXTRA1_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
.image_info.image_base = BL32_BASE,
.image_info.image_max_size = BL32_SIZE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
{
/* This is a zero sized image so we don't set base or size */
.image_id = BL32_EXTRA2_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
},
{
.image_id = BL33_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
entry_point_info_t,
NON_SECURE | EXECUTABLE),
# ifdef PRELOADED_BL33_BASE
.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
# else
.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = PLAT_NS_IMAGE_OFFSET,
.image_info.image_max_size = PLAT_NS_IMAGE_SIZE,
# endif /* PRELOADED_BL33_BASE */
.next_handoff_image_id = INVALID_IMAGE_ID,
}
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);

15
plat/imx/imx8m/imx8mp/imx8mp_rotpk.S Normal file
View File

@ -0,0 +1,15 @@
/*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
.global imx8mp_rotpk_hash
.global imx8mp_rotpk_hash_end
imx8mp_rotpk_hash:
/* DER header */
.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
/* SHA256 */
.incbin ROTPK_HASH
imx8mp_rotpk_hash_end:

36
plat/imx/imx8m/imx8mp/imx8mp_trusted_boot.c Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/common/platform.h>
extern char imx8mp_rotpk_hash[], imx8mp_rotpk_hash_end[];
int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
unsigned int *flags)
{
*key_ptr = imx8mp_rotpk_hash;
*key_len = imx8mp_rotpk_hash_end - imx8mp_rotpk_hash;
*flags = ROTPK_IS_HASH;
return 0;
}
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
{
*nv_ctr = 0;
return 0;
}
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
{
return 1;
}
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
return get_mbedtls_heap_helper(heap_addr, heap_size);
}

15
plat/imx/imx8m/imx8mp/include/imx8mp_private.h Normal file
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@ -0,0 +1,15 @@
/*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef IMX8MP_PRIVATE_H
#define IMX8MP_PRIVATE_H
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void plat_imx_io_setup(void);
#endif /* IMX8MP_PRIVATE_H */

21
plat/imx/imx8m/imx8mp/include/platform_def.h
View File

@ -6,6 +6,7 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <common/tbbr/tbbr_img_def.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
@ -34,8 +35,23 @@
#define PLAT_WAIT_RET_STATE U(1)
#define PLAT_STOP_OFF_STATE U(3)
#if defined(NEED_BL2)
#define BL2_BASE U(0x960000)
#define BL2_LIMIT U(0x980000)
#define BL31_BASE U(0x940000)
#define BL31_LIMIT U(0x960000)
#define IMX_FIP_BASE U(0x40310000)
#define IMX_FIP_SIZE U(0x000300000)
#define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE)
/* Define FIP image location on eMMC */
#define IMX_FIP_MMC_BASE U(0x100000)
#define PLAT_IMX8MP_BOOT_MMC_BASE U(0x30B50000) /* SD */
#else
#define BL31_BASE U(0x960000)
#define BL31_LIMIT U(0x980000)
#endif
#define PLAT_PRI_BITS U(3)
#define PLAT_SDEI_CRITICAL_PRI 0x10
@ -44,6 +60,7 @@
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
#define PLAT_NS_IMAGE_SIZE U(0x00200000)
/* GICv3 base address */
#define PLAT_GICD_BASE U(0x38800000)
@ -150,6 +167,10 @@
#define IMX_WDOG_B_RESET
#define MAX_IO_HANDLES 3U
#define MAX_IO_DEVICES 2U
#define MAX_IO_BLOCK_DEVICES 1U
#define GIC_MAP MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW)
#define AIPS_MAP MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW) /* AIPS map */
#define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_MEMORY | MT_RW) /* OCRAM_S */

94
plat/imx/imx8m/imx8mp/platform.mk
View File

@ -6,7 +6,9 @@
PLAT_INCLUDES := -Iplat/imx/common/include \
-Iplat/imx/imx8m/include \
-Iplat/imx/imx8m/imx8mp/include
-Iplat/imx/imx8m/imx8mp/include \
-Idrivers/imx/usdhc \
-Iinclude/common/tbbr
# Translation tables library
include lib/xlat_tables_v2/xlat_tables.mk
@ -40,6 +42,96 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \
${IMX_GIC_SOURCES} \
${XLAT_TABLES_LIB_SRCS}
ifeq (${NEED_BL2},yes)
BL2_SOURCES += common/desc_image_load.c \
plat/imx/common/imx8_helpers.S \
plat/imx/common/imx_uart_console.S \
plat/imx/imx8m/imx8mp/imx8mp_bl2_el3_setup.c \
plat/imx/imx8m/imx8mp/gpc.c \
plat/imx/imx8m/imx_aipstz.c \
plat/imx/imx8m/imx_rdc.c \
plat/imx/imx8m/imx8m_caam.c \
plat/common/plat_psci_common.c \
lib/cpus/aarch64/cortex_a53.S \
drivers/arm/tzc/tzc380.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
${PLAT_GIC_SOURCES} \
${PLAT_DRAM_SOURCES} \
${XLAT_TABLES_LIB_SRCS} \
drivers/mmc/mmc.c \
drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
drivers/imx/usdhc/imx_usdhc.c \
plat/imx/imx8m/imx8mp/imx8mp_bl2_mem_params_desc.c \
plat/imx/common/imx_io_storage.c \
plat/imx/imx8m/imx8m_image_load.c \
lib/optee/optee_utils.c
endif
# Add the build options to pack BLx images and kernel device tree
# in the FIP if the platform requires.
ifneq ($(BL2),)
RESET_TO_BL31 := 0
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
endif
ifneq ($(BL32_EXTRA1),)
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
endif
ifneq ($(BL32_EXTRA2),)
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
endif
ifneq ($(HW_CONFIG),)
$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
endif
ifeq (${NEED_BL2},yes)
$(eval $(call add_define,NEED_BL2))
LOAD_IMAGE_V2 := 1
# Non-TF Boot ROM
BL2_AT_EL3 := 1
endif
ifneq (${TRUSTED_BOARD_BOOT},0)
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
drivers/auth/tbbr/tbbr_cot_common.c \
drivers/auth/tbbr/tbbr_cot_bl2.c
BL2_SOURCES += ${AUTH_SOURCES} \
plat/common/tbbr/plat_tbbr.c \
plat/imx/imx8m/imx8mp/imx8mp_trusted_boot.c \
plat/imx/imx8m/imx8mp/imx8mp_rotpk.S
ROT_KEY = $(BUILD_PLAT)/rot_key.pem
ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
$(eval $(call MAKE_LIB_DIRS))
$(BUILD_PLAT)/bl2/imx8mp_rotpk.o: $(ROTPK_HASH)
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
@echo " OPENSSL $@"
@if [ ! -f $(ROT_KEY) ]; then \
openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
@echo " OPENSSL $@"
$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
USE_COHERENT_MEM := 1
RESET_TO_BL31 := 1
A53_DISABLE_NON_TEMPORAL_HINT := 0