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Merge changes from topic "rd_updates" into integration 

* changes:
  plat/sgi: allow usage of secure partions on rdn2 platform
  board/rdv1mc: initialize tzc400 controllers
  plat/sgi: allow access to TZC controller on all chips
  plat/sgi: define memory regions for multi-chip platforms
  plat/sgi: allow access to nor2 flash and system registers from s-el0
  plat/sgi: define default list of memory regions for dmc620 tzc
  plat/sgi: improve macros defining cper buffer memory region
  plat/sgi: refactor DMC-620 error handling SMC function id
  plat/sgi: refactor SDEI specific macros
This commit is contained in:
Madhukar Pappireddy 2021-03-29 20:42:49 +02:00 committed by TrustedFirmware Code Review
parent 27d593ad95 c0d55ef7c0
commit cba9c0c2aa
18 changed files with 377 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
plat/arm/board/rde1edge/include/platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, Arm Limited. All rights reserved.
* Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,6 +9,7 @@
#include <lib/utils_def.h>
#include <sgi_sdei.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)

10
plat/arm/board/rde1edge/rde1edge_security.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
* Copyright (c) 2019-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,7 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc_dmc620.h>
#include <sgi_dmc620_tzc_regions.h>
uintptr_t rde1edge_dmc_base[] = {
RDE1EDGE_DMC620_BASE0,
@ -20,11 +20,7 @@ static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
};
static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {

3
plat/arm/board/rdn1edge/include/platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,6 +9,7 @@
#include <lib/utils_def.h>
#include <sgi_sdei.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)

10
plat/arm/board/rdn1edge/rdn1edge_security.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, ARM Limited. All rights reserved.
* Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,7 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc_dmc620.h>
#include <sgi_dmc620_tzc_regions.h>
uintptr_t rdn1edge_dmc_base[] = {
RDN1EDGE_DMC620_BASE0,
@ -20,11 +20,7 @@ static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = {
};
static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {

25
plat/arm/board/rdv1mc/include/platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -20,6 +20,29 @@
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x21830000)
#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
(n * TZC400_OFFSET))
#define TZC400_OFFSET UL(0x1000000)
#define TZC400_COUNT U(8)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define TZC_NSAID_ALL_AP U(0)
#define TZC_NSAID_PCI U(1)
#define TZC_NSAID_HDLCD0 U(2)
#define TZC_NSAID_CLCD U(7)
#define TZC_NSAID_AP U(9)
#define TZC_NSAID_VIRTIO U(15)
#define PLAT_ARM_TZC_NS_DEV_ACCESS \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)

4
plat/arm/board/rdv1mc/platform.mk
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@ -1,4 +1,4 @@
# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -23,6 +23,8 @@ BL1_SOURCES += ${SGI_CPU_SOURCES} \
BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_plat.c \
${RDV1MC_BASE}/rdv1mc_security.c \
${RDV1MC_BASE}/rdv1mc_err.c \
drivers/arm/tzc/tzc400.c \
plat/arm/common/arm_tzc400.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c

56
plat/arm/board/rdv1mc/rdv1mc_security.c
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@ -1,10 +1,64 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
/* TZC memory regions for the first chip */
static const arm_tzc_regions_info_t tzc_regions[] = {
ARM_TZC_REGIONS_DEF,
{}
};
#if CSS_SGI_CHIP_COUNT > 1
static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
{
/* TZC memory regions for second chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
{}
},
#if CSS_SGI_CHIP_COUNT > 2
{
/* TZC memory regions for third chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
{}
},
#endif
#if CSS_SGI_CHIP_COUNT > 3
{
/* TZC memory regions for fourth chip */
SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
{}
},
#endif
};
#endif /* CSS_SGI_CHIP_COUNT */
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
unsigned int i;
INFO("Configuring TrustZone Controller for Chip 0\n");
for (i = 0; i < TZC400_COUNT; i++) {
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
}
#if CSS_SGI_CHIP_COUNT > 1
unsigned int j;
for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
INFO("Configuring TrustZone Controller for Chip %u\n", i);
for (j = 0; j < TZC400_COUNT; j++) {
arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
+ TZC400_BASE(j), tzc_regions_mc[i-1]);
}
}
#endif
}

3
plat/arm/board/sgi575/include/platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,6 +9,7 @@
#include <lib/utils_def.h>
#include <sgi_sdei.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)

11
plat/arm/board/sgi575/sgi575_security.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,8 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/arm/tzc_dmc620.h>
#include <plat/arm/common/plat_arm.h>
#include <sgi_dmc620_tzc_regions.h>
uintptr_t sgi575_dmc_base[] = {
SGI575_DMC620_BASE0,
@ -21,11 +20,7 @@ static const tzc_dmc620_driver_data_t sgi575_plat_driver_data = {
};
static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
{
.region_base = ARM_AP_TZC_DRAM1_BASE,
.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
.sec_attr = TZC_DMC620_REGION_S_RDWR
}
CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t sgi575_plat_config_data = {

114
plat/arm/css/sgi/include/sgi_base_platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -26,14 +26,17 @@
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
* plat_arm_mmap array defined for each BL stage. In addition to that, on
* multi-chip platforms, address regions on each of the remote chips are
* also mapped. In BL31, for instance, three address regions on the remote
* chips are accessed - secure ram, css device and soc device regions.
*/
#if defined(IMAGE_BL31)
# if SPM_MM
# define PLAT_ARM_MMAP_ENTRIES 9
# define MAX_XLAT_TABLES 7
# define PLAT_SP_IMAGE_MMAP_REGIONS 7
# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
# define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
# define PLAT_SP_IMAGE_MMAP_REGIONS 9
# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 11
# else
# define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
@ -41,6 +44,17 @@
#elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 5
#elif defined(IMAGE_BL2)
# define PLAT_ARM_MMAP_ENTRIES (11 + (CSS_SGI_CHIP_COUNT - 1))
/*
* MAX_XLAT_TABLES entries need to be doubled because when the address width
* exceeds 40 bits an additional level of translation is required. In case of
* multichip platforms peripherals also fall into address space with width
* > 40 bits
*
*/
# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 2))
#elif !USE_ROMLIB
# define PLAT_ARM_MMAP_ENTRIES 11
# define MAX_XLAT_TABLES 7
@ -69,12 +83,17 @@
/*
* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
* little space for growth.
* little space for growth. Additional 8KiB space is added per chip in
* order to accommodate the additional level of translation required for "TZC"
* peripheral access which lies in >4TB address space.
*
*/
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
# define PLAT_ARM_MAX_BL2_SIZE (0x1D000 + ((CSS_SGI_CHIP_COUNT - 1) * \
0x2000))
#else
# define PLAT_ARM_MAX_BL2_SIZE 0x14000
# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((CSS_SGI_CHIP_COUNT - 1) * \
0x2000))
#endif
/*
@ -165,48 +184,36 @@
#define PLAT_SP_PRI PLAT_RAS_PRI
#if RAS_EXTENSION
/* Allocate 128KB for CPER buffers */
#define PLAT_SP_BUF_BASE ULL(0x20000)
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE + \
PLAT_SP_BUF_BASE)
/* Platform specific SMC FID's used for RAS */
#define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042
#define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042
#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043
#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043
#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044
#define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044
/* ARM SDEI dynamic shared event numbers */
#define SGI_SDEI_DS_EVENT_0 804
#define SGI_SDEI_DS_EVENT_1 805
#define PLAT_ARM_PRIVATE_SDEI_EVENTS \
SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \
SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL),
#define PLAT_ARM_SHARED_SDEI_EVENTS
#define ARM_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
#define ARM_SP_CPER_BUF_SIZE ULL(0x20000)
#define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \
ARM_SP_CPER_BUF_BASE, \
ARM_SP_CPER_BUF_BASE, \
ARM_SP_CPER_BUF_SIZE, \
MT_RW_DATA | MT_NS | MT_USER, \
#if SPM_MM && RAS_EXTENSION
/*
* CPER buffer memory of 128KB is reserved and it is placed adjacent to the
* memory shared between EL3 and S-EL0.
*/
#define CSS_SGI_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
#define CSS_SGI_SP_CPER_BUF_SIZE ULL(0x20000)
#define CSS_SGI_SP_CPER_BUF_MMAP MAP_REGION2( \
CSS_SGI_SP_CPER_BUF_BASE, \
CSS_SGI_SP_CPER_BUF_BASE, \
CSS_SGI_SP_CPER_BUF_SIZE, \
MT_RW_DATA | MT_NS | MT_USER, \
PAGE_SIZE)
#else
/*
* Secure partition stack follows right after the memory space reserved for
* CPER buffer memory.
*/
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE + \
CSS_SGI_SP_CPER_BUF_SIZE)
#elif SPM_MM
/*
* Secure partition stack follows right after the memory region that is shared
* between EL3 and S-EL0.
*/
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
#endif /* RAS_EXTENSION */
#endif /* SPM_MM && RAS_EXTENSION */
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
@ -238,4 +245,17 @@
/* Number of SCMI channels on the platform */
#define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT
/*
* Mapping definition of the TrustZone Controller for ARM SGI/RD platforms
* where both the DRAM regions are marked for non-secure access. This applies
* to multi-chip platforms.
*/
#define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \
{CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
{CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
#endif /* SGI_BASE_PLATFORM_DEF_H */

36
plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SGI_DMC620_TZC_REGIONS_H
#define SGI_DMC620_TZC_REGIONS_H
#include <drivers/arm/tzc_dmc620.h>
#if SPM_MM
#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
{ \
.region_base = ARM_AP_TZC_DRAM1_BASE, \
.region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \
.sec_attr = TZC_DMC620_REGION_S_RDWR \
}, { \
.region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \
.region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \
.sec_attr = TZC_DMC620_REGION_S_NS_RDWR \
}, { \
.region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \
.region_top = ARM_AP_TZC_DRAM1_END, \
.sec_attr = TZC_DMC620_REGION_S_RDWR \
}
#else
#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
{ \
.region_base = ARM_AP_TZC_DRAM1_BASE, \
.region_top = ARM_AP_TZC_DRAM1_END, \
.sec_attr = TZC_DMC620_REGION_S_RDWR \
}
#endif /* SPM_MM */
#endif /* SGI_DMC620_TZC_REGIONS_H */

6
plat/arm/css/sgi/include/sgi_ras.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,6 +7,10 @@
#ifndef SGI_RAS_H
#define SGI_RAS_H
/* Platform specific SMC FID's used for DMC-620 RAS error handling */
#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043
#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044
/*
* Mapping the RAS interrupt with SDEI event number and the event
* id used with Standalone MM code

25
plat/arm/css/sgi/include/sgi_sdei.h Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SGI_SDEI_H
#define SGI_SDEI_H
#if SDEI_SUPPORT
/* ARM SDEI dynamic shared event numbers */
#define SGI_SDEI_DS_EVENT_0 U(804)
#define SGI_SDEI_DS_EVENT_1 U(805)
#define PLAT_ARM_PRIVATE_SDEI_EVENTS \
SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \
SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL),
#define PLAT_ARM_SHARED_SDEI_EVENTS
#endif /* SDEI_SUPPORT */
#endif /* SGI_SDEI_H */

14
plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -70,6 +70,18 @@
SOC_PLATFORM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#if SPM_MM
/*
* Memory map definition for the platform peripheral memory region that is
* accessible from S-EL0 (with secure user mode access).
*/
#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \
MAP_REGION_FLAT( \
SOC_PLATFORM_PERIPH_BASE, \
SOC_PLATFORM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#endif
#define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
SOC_SYSTEM_PERIPH_BASE, \
SOC_SYSTEM_PERIPH_SIZE, \

20
plat/arm/css/sgi/include/sgi_soc_platform_def.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,4 +12,22 @@
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/soc/common/soc_css_def.h>
/* Map the System registers to access from S-EL0 */
#define CSS_SYSTEMREG_DEVICE_BASE (0x1C010000)
#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000)
#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \
CSS_SYSTEMREG_DEVICE_BASE, \
CSS_SYSTEMREG_DEVICE_SIZE, \
(MT_DEVICE | MT_RW | \
MT_SECURE | MT_USER))
/* Map the NOR2 Flash to access from S-EL0 */
#define CSS_NOR2_FLASH_DEVICE_BASE (0x10000000)
#define CSS_NOR2_FLASH_DEVICE_SIZE (0x04000000)
#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \
CSS_NOR2_FLASH_DEVICE_BASE, \
CSS_NOR2_FLASH_DEVICE_SIZE, \
(MT_DEVICE | MT_RW | \
MT_SECURE | MT_USER))
#endif /* SGI_SOC_PLATFORM_DEF_H */

20
plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,4 +10,22 @@
#include <sgi_base_platform_def.h>
#include <sgi_soc_css_def_v2.h>
/* Map the System registers to access from S-EL0 */
#define CSS_SYSTEMREG_DEVICE_BASE (0x0C010000)
#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000)
#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \
CSS_SYSTEMREG_DEVICE_BASE, \
CSS_SYSTEMREG_DEVICE_SIZE, \
(MT_DEVICE | MT_RW | \
MT_SECURE | MT_USER))
/* Map the NOR2 Flash to access from S-EL0 */
#define CSS_NOR2_FLASH_DEVICE_BASE (0x001054000000)
#define CSS_NOR2_FLASH_DEVICE_SIZE (0x000004000000)
#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \
CSS_NOR2_FLASH_DEVICE_BASE, \
CSS_NOR2_FLASH_DEVICE_SIZE, \
(MT_DEVICE | MT_RW | \
MT_SECURE | MT_USER))
#endif /* SGI_SOC_PLATFORM_DEF_V2_H */

17
plat/arm/css/sgi/sgi_plat.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -49,6 +49,15 @@ const mmap_region_t plat_arm_mmap[] = {
CSS_SGI_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
#if CSS_SGI_CHIP_COUNT > 1
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
#endif
#if CSS_SGI_CHIP_COUNT > 2
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
#endif
#if CSS_SGI_CHIP_COUNT > 3
CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
@ -78,10 +87,14 @@ const mmap_region_t plat_arm_mmap[] = {
#if SPM_MM && defined(IMAGE_BL31)
const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_ARM_SECURE_MAP_SYSTEMREG,
PLAT_ARM_SECURE_MAP_NOR2,
PLAT_ARM_SECURE_MAP_DEVICE,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
ARM_SP_CPER_BUF_MMAP,
#if RAS_EXTENSION
CSS_SGI_SP_CPER_BUF_MMAP,
#endif
ARM_SP_IMAGE_RW_MMAP,
ARM_SPM_BUF_EL0_MMAP,
{0}

82
plat/arm/css/sgi/sgi_plat_v2.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,6 +12,10 @@
#include <plat/common/platform.h>
#include <drivers/arm/sbsa.h>
#if SPM_MM
#include <services/spm_mm_partition.h>
#endif
/*
* Table of regions for different BL stages to map using the MMU.
*/
@ -41,6 +45,9 @@ const mmap_region_t plat_arm_mmap[] = {
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
ARM_MAP_BL1_RW,
#endif
@ -57,13 +64,86 @@ const mmap_region_t plat_arm_mmap[] = {
CSS_SGI_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
{0}
};
#if SPM_MM && defined(IMAGE_BL31)
const mmap_region_t plat_arm_secure_partition_mmap[] = {
PLAT_ARM_SECURE_MAP_SYSTEMREG,
PLAT_ARM_SECURE_MAP_NOR2,
SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
ARM_SP_IMAGE_RW_MMAP,
ARM_SPM_BUF_EL0_MMAP,
{0}
};
#endif /* SPM_MM && defined(IMAGE_BL31) */
#endif
ARM_CASSERT_MMAP
#if SPM_MM && defined(IMAGE_BL31)
/*
* Boot information passed to a secure partition during initialisation. Linear
* indices in MP information will be filled at runtime.
*/
static spm_mm_mp_info_t sp_mp_info[] = {
[0] = {0x81000000, 0},
[1] = {0x81010000, 0},
[2] = {0x81020000, 0},
[3] = {0x81030000, 0},
[4] = {0x81040000, 0},
[5] = {0x81050000, 0},
[6] = {0x81060000, 0},
[7] = {0x81070000, 0},
[8] = {0x81080000, 0},
[9] = {0x81090000, 0},
[10] = {0x810a0000, 0},
[11] = {0x810b0000, 0},
[12] = {0x810c0000, 0},
[13] = {0x810d0000, 0},
[14] = {0x810e0000, 0},
[15] = {0x810f0000, 0},
};
const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
.h.version = VERSION_1,
.h.size = sizeof(spm_mm_boot_info_t),
.h.attr = 0,
.sp_mem_base = ARM_SP_IMAGE_BASE,
.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
.sp_image_base = ARM_SP_IMAGE_BASE,
.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
.sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
.sp_image_size = ARM_SP_IMAGE_SIZE,
.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
.sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
.num_cpus = PLATFORM_CORE_COUNT,
.mp_info = &sp_mp_info[0],
};
const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
{
return plat_arm_secure_partition_mmap;
}
const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
void *cookie)
{
return &plat_arm_secure_partition_boot_info;
}
#endif /* SPM_MM && defined(IMAGE_BL31) */
#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{