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Merge changes from topic "jc/shift-overflow" into integration 

* changes:
  Enable -Wshift-overflow=2 to check for undefined shift behavior
  Update base code to not rely on undefined overflow behaviour
  Update hisilicon drivers to not rely on undefined overflow behaviour
  Update synopsys drivers to not rely on undefined overflow behaviour
  Update imx platform to not rely on undefined overflow behaviour
  Update mediatek platform to not rely on undefined overflow behaviour
  Update layerscape platform to not rely on undefined overflow behaviour
  Update intel platform to not rely on undefined overflow behaviour
  Update rockchip platform to not rely on undefined overflow behaviour
  Update renesas platform to not rely on undefined overflow behaviour
  Update meson platform to not rely on undefined overflow behaviour
  Update marvell platform to not rely on undefined overflow behaviour
This commit is contained in:
Soby Mathew 2019-07-16 10:11:27 +00:00 committed by TrustedFirmware Code Review
parent dc150425c3 93c690eba8
commit d0d0f17164
37 changed files with 120 additions and 114 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Makefile
View File

@ -256,9 +256,14 @@ WARNINGS += -Wunused -Wno-unused-parameter \
-Wvla
ifeq ($(findstring clang,$(notdir $(CC))),)
# not using clang
WARNINGS += -Wunused-but-set-variable \
-Wmaybe-uninitialized \
-Wpacked-bitfield-compat
-Wpacked-bitfield-compat \
-Wshift-overflow=2
else
# using clang
WARNINGS += -Wshift-overflow -Wshift-sign-overflow
endif
ifneq (${E},0)

2
drivers/marvell/mci.c
View File

@ -245,7 +245,7 @@
MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET)
#define MCI_PHY_CTRL_PIDI_MODE_OFFSET 31
#define MCI_PHY_CTRL_PIDI_MODE \
(1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
(1U << MCI_PHY_CTRL_PIDI_MODE_OFFSET)
/* Number of times to wait for the MCI link ready after MCI configurations
* Normally takes 34-35 successive reads

4
drivers/marvell/mochi/cp110_setup.c
View File

@ -56,11 +56,11 @@
(0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET)
#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16
#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \
(0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
(0xffffu << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET)
#define MVEBU_SAMPLE_AT_RESET_REG (0x440600)
#define SAR_PCIE1_CLK_CFG_OFFSET 31
#define SAR_PCIE1_CLK_CFG_MASK (0x1 << SAR_PCIE1_CLK_CFG_OFFSET)
#define SAR_PCIE1_CLK_CFG_MASK (0x1u << SAR_PCIE1_CLK_CFG_OFFSET)
#define SAR_PCIE0_CLK_CFG_OFFSET 30
#define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET)
#define SAR_I2C_INIT_EN_OFFSET 24

6
drivers/meson/gxl/crypto/sha_dma.c
View File

@ -104,8 +104,8 @@ struct asd_desc {
#define ASD_DESC_ERR_SET(d, v) \
(ASD_DESC_SET((d)->cfg, v, ASD_DESC_ERR_MASK, ASD_DESC_ERR_OFF))
#define ASD_DESC_OWNER_OFF 31
#define ASD_DESC_OWNER_MASK 0x1
#define ASD_DESC_OWNER_OFF 31u
#define ASD_DESC_OWNER_MASK 0x1u
#define ASD_DESC_OWNER(d) \
(ASD_DESC_GET((d)->cfg, ASD_DESC_OWNER_MASK, ASD_DESC_OWNER_OFF))
#define ASD_DESC_OWNER_SET(d, v) \
@ -126,7 +126,7 @@ static void asd_compute_sha(struct asd_ctx *ctx, void *data, size_t len,
assert((uintptr_t)&desc == (uintptr_t)&desc);
ASD_DESC_LEN_SET(&desc, len);
ASD_DESC_OWNER_SET(&desc, 1);
ASD_DESC_OWNER_SET(&desc, 1u);
ASD_DESC_ENCONLY_SET(&desc, 1);
ASD_DESC_EOD_SET(&desc, 1);
if (ctx->started == 0) {

2
drivers/renesas/rcar/cpld/ulcb_cpld.c
View File

@ -68,7 +68,7 @@ static void cpld_write(uint8_t addr, uint32_t data)
for (i = 0; i < 32; i++) {
/* MSB first */
gpio_set_value(GPIO_OUTDT6, MOSI, data & (1 << 31));
gpio_set_value(GPIO_OUTDT6, MOSI, data & (1U << 31));
gpio_set_value(GPIO_OUTDT6, SCLK, 1);
data <<= 1;
gpio_set_value(GPIO_OUTDT6, SCLK, 0);

6
drivers/renesas/rcar/pwrc/pwrc.c
View File

@ -763,10 +763,10 @@ uint32_t rcar_pwrc_get_cluster(void)
reg = mmio_read_32(RCAR_PRR);
if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
return RCAR_CLUSTER_CA57;
if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
return RCAR_CLUSTER_CA53;
return RCAR_CLUSTER_A53A57;
@ -810,7 +810,7 @@ uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
count_ca57:
if (IS_A53A57(c) || IS_CA57(c)) {
if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
goto done;
for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {

2
drivers/renesas/rcar/pwrc/pwrc.h
View File

@ -15,7 +15,7 @@
#define PWKUPR_WEN (1ull << 31)
#define PSYSR_AFF_L2 (1 << 31)
#define PSYSR_AFF_L2 (1U << 31)
#define PSYSR_AFF_L1 (1 << 30)
#define PSYSR_AFF_L0 (1 << 29)
#define PSYSR_WEN (1 << 28)

5
drivers/synopsys/emmc/dw_mmc.c
View File

@ -14,6 +14,7 @@
#include <drivers/delay_timer.h>
#include <drivers/mmc.h>
#include <drivers/synopsys/dw_mmc.h>
#include <lib/utils_def.h>
#include <lib/mmio.h>
#define DWMMC_CTRL (0x00)
@ -55,7 +56,7 @@
#define DWMMC_CMDARG (0x28)
#define DWMMC_CMD (0x2c)
#define CMD_START (1 << 31)
#define CMD_START (U(1) << 31)
#define CMD_USE_HOLD_REG (1 << 29) /* 0 if SDR50/100 */
#define CMD_UPDATE_CLK_ONLY (1 << 21)
#define CMD_SEND_INIT (1 << 15)
@ -100,7 +101,7 @@
#define IDMAC_DES0_CH (1 << 4)
#define IDMAC_DES0_ER (1 << 5)
#define IDMAC_DES0_CES (1 << 30)
#define IDMAC_DES0_OWN (1 << 31)
#define IDMAC_DES0_OWN (U(1) << 31)
#define IDMAC_DES1_BS1(x) ((x) & 0x1fff)
#define IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13)

2
include/drivers/ufs.h
View File

@ -82,7 +82,7 @@
#define UECDME 0x48
/* UTP Transfer Request Interrupt Aggregation Control Register */
#define UTRIACR 0x4C
#define UTRIACR_IAEN (1 << 31)
#define UTRIACR_IAEN (1U << 31)
#define UTRIACR_IAPWEN (1 << 24)
#define UTRIACR_IASB (1 << 20)
#define UTRIACR_CTR (1 << 16)

4
lib/xlat_tables/aarch32/nonlpae_tables.c
View File

@ -122,8 +122,8 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
#define DACR_DOMAIN_PERM_CLIENT 0x1
#define DACR_DOMAIN_PERM_MANAGER 0x3
#define NUM_1MB_IN_4GB (1 << 12)
#define NUM_4K_IN_1MB (1 << 8)
#define NUM_1MB_IN_4GB (1U << 12)
#define NUM_4K_IN_1MB (1U << 8)
#define ONE_MB_SHIFT 20

2
plat/hisilicon/hikey/hikey_ddr.c
View File

@ -138,7 +138,7 @@ static void init_freq(void)
mmio_write_32((0xf6504000 + 0x06c), data);
data = mmio_read_32((0xf6504000 + 0x06c));
data &= ~(0xffffff << 8);
data &= ~(0xffffffu << 8);
data |= 0xc7a << 8;
mmio_write_32((0xf6504000 + 0x06c), data);

8
plat/hisilicon/hikey/include/hi6220_regs_ao.h
View File

@ -222,14 +222,14 @@
#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31)
#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1U << 31)
#define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
#define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
#define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
#define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
#define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31)
#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1U << 31)
#define AO_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
#define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
@ -237,7 +237,7 @@
#define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
#define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
#define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31)
#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1U << 31)
#define AO_SC_SYS_STAT1_MODE_STATUS (1 << 0)
#define AO_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
@ -308,7 +308,7 @@
#define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH (1 << 28)
#define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON (1 << 29)
#define AO_SC_PERIPH_CLKEN4_CLK_PDM (1 << 30)
#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1 << 31)
#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1U << 31)
#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU (1 << 0)
#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU (1 << 1)

2
plat/hisilicon/hikey/include/hi6220_regs_peri.h
View File

@ -134,7 +134,7 @@
#define PERI_CTRL4_OTG_SESSEND (1 << 28)
#define PERI_CTRL4_OTG_BVALID (1 << 29)
#define PERI_CTRL4_OTG_AVALID (1 << 30)
#define PERI_CTRL4_OTG_VBUSVALID (1 << 31)
#define PERI_CTRL4_OTG_VBUSVALID (1U << 31)
/* PERI_SC_PERIPH_CTRL5 */
#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)

2
plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c
View File

@ -23,7 +23,7 @@
#define RES2_LOCK_BASE (SOC_PCTRL_RESOURCE2_LOCK_ADDR(PCTRL_BASE))
#define LOCK_BIT (0x1 << 28)
#define LOCK_ID_MASK (0x7 << 29)
#define LOCK_ID_MASK (0x7u << 29)
#define CPUIDLE_LOCK_ID(core) (0x6 - (core))
#define LOCK_UNLOCK_OFFSET 0x4
#define LOCK_STAT_OFFSET 0x8

2
plat/hisilicon/hikey960/include/hi3660.h
View File

@ -67,7 +67,7 @@
#define SCTRL_SCPERDIS1_REG (SCTRL_REG_BASE + 0x174)
#define SCTRL_SCPEREN1_REG (SCTRL_REG_BASE + 0x170)
#define SCTRL_SCPERDIS1_REG (SCTRL_REG_BASE + 0x174)
#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS (1 << 31)
#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS (1u << 31)
#define SCPEREN_GT_PCLK_MMBUFCFG (1 << 25)
#define SCPEREN_GT_PCLK_MMBUF (1 << 23)
#define SCPEREN_GT_ACLK_MMBUF (1 << 22)

4
plat/hisilicon/hikey960/include/hi3660_crg.h
View File

@ -11,7 +11,7 @@
#define CRG_PEREN0_REG (CRG_REG_BASE + 0x000)
#define CRG_PERDIS0_REG (CRG_REG_BASE + 0x004)
#define CRG_PERSTAT0_REG (CRG_REG_BASE + 0x008)
#define PEREN0_GT_CLK_AOMM (1 << 31)
#define PEREN0_GT_CLK_AOMM (1U << 31)
#define CRG_PEREN1_REG (CRG_REG_BASE + 0x010)
#define CRG_PERDIS1_REG (CRG_REG_BASE + 0x014)
@ -62,7 +62,7 @@
#define CRG_PERRSTSTAT5_REG (CRG_REG_BASE + 0x0A4)
/* bit fields in CRG_PERI */
#define PERI_PCLK_PCTRL_BIT (1 << 31)
#define PERI_PCLK_PCTRL_BIT (1U << 31)
#define PERI_TIMER12_BIT (1 << 25)
#define PERI_TIMER11_BIT (1 << 24)
#define PERI_TIMER10_BIT (1 << 23)

4
plat/hisilicon/hikey960/include/hi3660_hkadc.h
View File

@ -13,7 +13,7 @@
#define HKADC_DSP_START_CLR_REG (HKADC_SSI_REG_BASE + 0x01C)
#define HKADC_WR01_DATA_REG (HKADC_SSI_REG_BASE + 0x020)
#define WR1_WRITE_MODE (1 << 31)
#define WR1_WRITE_MODE (1U << 31)
#define WR1_READ_MODE (0 << 31)
#define WR1_ADDR(x) (((x) & 0x7F) << 24)
#define WR1_DATA(x) (((x) & 0xFF) << 16)
@ -47,7 +47,7 @@
#define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | \
(0x1 << 16))
#define HKADC_WR23_VALUE ((0x1 << 31) | \
#define HKADC_WR23_VALUE ((0x1u << 31) | \
(HKADC_DATA0_ADDR << 24) | \
(1 << 15) | \
(HKADC_DATA1_ADDR << 8))

4
plat/imx/common/sci/imx8_mu.h
View File

@ -13,7 +13,7 @@
#define MU_TR_COUNT1 4
#define MU_RR_COUNT1 4
#define MU_CR_GIEn_MASK1 (0xF << 28)
#define MU_CR_GIEn_MASK1 (0xFu << 28)
#define MU_CR_RIEn_MASK1 (0xF << 24)
#define MU_CR_TIEn_MASK1 (0xF << 20)
#define MU_CR_GIRn_MASK1 (0xF << 16)
@ -23,7 +23,7 @@
#define MU_SR_TE0_MASK1 (1 << 23)
#define MU_SR_RF0_MASK1 (1 << 27)
#define MU_CR_RIE0_MASK1 (1 << 27)
#define MU_CR_GIE0_MASK1 (1 << 31)
#define MU_CR_GIE0_MASK1 (1U << 31)
#define MU_TR_COUNT 4
#define MU_RR_COUNT 4

2
plat/intel/soc/common/drivers/qspi/cadence_qspi.h
View File

@ -34,7 +34,7 @@
#define CAD_QSPI_CFG_CS(x) (((x) << 11))
#define CAD_QSPI_CFG_ENABLE (1 << 0)
#define CAD_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
#define CAD_QSPI_CFG_IDLE (1 << 31)
#define CAD_QSPI_CFG_IDLE (1U << 31)
#define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
#define CAD_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd

2
plat/intel/soc/stratix10/include/s10_mailbox.h
View File

@ -76,7 +76,7 @@
#define RECONFIG_STATUS_STATE 0
#define RECONFIG_STATUS_PIN_STATUS 2
#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
#define PIN_STATUS_NSTATUS (1 << 31)
#define PIN_STATUS_NSTATUS (1U << 31)
#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)

4
plat/layerscape/board/ls1043/ls1043_psci.c
View File

@ -66,12 +66,12 @@ static void ls1043_reset_core(int core_pos)
dsb();
/* enable core soft reset */
mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORESRENCR_OFFSET,
htobe32(1 << 31));
htobe32(1U << 31));
dsb();
isb();
/* reset core */
mmio_write_32(LS_SCFG_BASE + LS_SCFG_CORE0_SFT_RST_OFFSET +
core_pos * 4, htobe32(1 << 31));
core_pos * 4, htobe32(1U << 31));
mdelay(10);
}

2
plat/layerscape/board/ls1043/ls_gic.c
View File

@ -35,7 +35,7 @@ void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
soc_dev_id == (SVR_LS1043AE << 8)) &&
((val & 0xff) == REV1_1)) {
val = be32toh(mmio_read_32((uintptr_t)gic_align));
if (val & (1 << GIC_ADDR_BIT)) {
if (val & (1U << GIC_ADDR_BIT)) {
*gicc_base = GICC_BASE;
*gicd_base = GICD_BASE;
} else {

6
plat/layerscape/common/include/soc.h
View File

@ -9,9 +9,9 @@
#include <stdint.h>
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1043A 0x879204
#define SVR_LS1043AE 0x879200
#define SVR_WO_E 0xFFFFFEu
#define SVR_LS1043A 0x879204u
#define SVR_LS1043AE 0x879200u
void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);

2
plat/marvell/a8k/common/include/a8k_plat_def.h
View File

@ -18,7 +18,7 @@
#define GWD_IIDR2_REV_ID_OFFSET 12
#define GWD_IIDR2_REV_ID_MASK 0xF
#define GWD_IIDR2_CHIP_ID_OFFSET 20
#define GWD_IIDR2_CHIP_ID_MASK (0xFFF << GWD_IIDR2_CHIP_ID_OFFSET)
#define GWD_IIDR2_CHIP_ID_MASK (0xFFFu << GWD_IIDR2_CHIP_ID_OFFSET)
#define CHIP_ID_AP806 0x806
#define CHIP_ID_AP807 0x807

4
plat/marvell/a8k/common/plat_ble_setup.c
View File

@ -77,13 +77,13 @@
/* VDD limit is 0.82V for all A3900 devices
* AVS offsets are not the same as in A70x0
*/
#define AVS_A3900_CLK_VALUE ((0x80 << 24) | \
#define AVS_A3900_CLK_VALUE ((0x80u << 24) | \
(0x2c2 << 13) | \
(0x2c2 << 3) | \
(0x1 << AVS_SOFT_RESET_OFFSET) | \
(0x1 << AVS_ENABLE_OFFSET))
/* VDD is 0.88V for 2GHz clock */
#define AVS_A3900_HIGH_CLK_VALUE ((0x80 << 24) | \
#define AVS_A3900_HIGH_CLK_VALUE ((0x80u << 24) | \
(0x2f5 << 13) | \
(0x2f5 << 3) | \
(0x1 << AVS_SOFT_RESET_OFFSET) | \

6
plat/marvell/a8k/common/plat_pm.c
View File

@ -93,7 +93,7 @@ enum CPU_ID {
#define PWRC_CPUN_CR_ISO_ENABLE_MASK \
(0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET)
#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK \
(0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)
(0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)
#define CCU_B_PRCRN_REG(cpu_id) \
(MVEBU_REGS_BASE + 0x1A50 + \
@ -253,7 +253,7 @@ static int plat_marvell_cpu_powerup(u_register_t mpidr)
/* 3. Assert power ready */
reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
reg_val |= 0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET;
reg_val |= 0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET;
mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val);
/* 4. Read & Validate power ready
@ -262,7 +262,7 @@ static int plat_marvell_cpu_powerup(u_register_t mpidr)
do {
reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id));
exit_loop--;
} while (!(reg_val & (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) &&
} while (!(reg_val & (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) &&
exit_loop > 0);
if (exit_loop <= 0)

2
plat/mediatek/mt8183/drivers/mcsi/mcsi.h
View File

@ -41,7 +41,7 @@
#define BD_CTRL_REG 0x40
/* Snoop Control register bit definitions */
#define DVM_SUPPORT (1 << 31)
#define DVM_SUPPORT (1U << 31)
#define SNP_SUPPORT (1 << 30)
#define SHAREABLE_OVWRT (1 << 2)
#define DVM_EN_BIT (1 << 1)

2
plat/mediatek/mt8183/include/mcucfg.h
View File

@ -197,7 +197,7 @@ enum {
MP0_CPUCFG_64BIT_SHIFT = 12,
MP1_CPUCFG_64BIT_SHIFT = 28,
MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
MP1_CPUCFG_64BIT = 0xfu << MP1_CPUCFG_64BIT_SHIFT
};
/* scu related */

2
plat/mediatek/mt8183/include/platform_def.h
View File

@ -180,7 +180,7 @@ INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
#define MTK_WDT_STATUS_SECURITY_RST (1 << 28)
#define MTK_WDT_STATUS_IRQ_ASSERT (1 << 29)
#define MTK_WDT_STATUS_SW_WDT_RST (1 << 30)
#define MTK_WDT_STATUS_HW_WDT_RST (1 << 31)
#define MTK_WDT_STATUS_HW_WDT_RST (1U << 31)
/* RGU other related */
#define MTK_WDT_MODE_DUAL_MODE 0x0040

4
plat/renesas/rcar/rcar_common.c
View File

@ -18,10 +18,10 @@
#define MSTP318 (1 << 18)
#define MSTP319 (1 << 19)
#define PMSR 0x5c
#define PMSR_L1FAEG (1 << 31)
#define PMSR_L1FAEG (1U << 31)
#define PMSR_PMEL1RX (1 << 23)
#define PMCTLR 0x60
#define PMSR_L1IATN (1 << 31)
#define PMSR_L1IATN (1U << 31)
static int rcar_pcie_fixup(unsigned int controller)
{

12
plat/rockchip/rk3328/drivers/pmu/pmu.c
View File

@ -284,7 +284,7 @@ static inline void pm_pll_wait_lock(uint32_t pll_id)
static inline void pll_pwr_dwn(uint32_t pll_id, uint32_t pd)
{
mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1),
BITS_WITH_WMASK(1, 1, 15));
BITS_WITH_WMASK(1U, 1U, 15));
if (pd)
mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1),
BITS_WITH_WMASK(1, 1, 14));
@ -305,7 +305,7 @@ static __sramfunc void dpll_suspend(void)
sram_data.dpll_con_save[i] =
mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, i));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(1, 1, 15));
BITS_WITH_WMASK(1U, 1U, 15));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(1, 1, 14));
}
@ -315,7 +315,7 @@ static __sramfunc void dpll_resume(void)
uint32_t delay = PLL_LOCKED_TIMEOUT;
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(1, 1, 15));
BITS_WITH_WMASK(1U, 1U, 15));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
BITS_WITH_WMASK(0, 1, 14));
mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1),
@ -402,7 +402,7 @@ static void pm_plls_suspend(void)
/* clk_rtc32k */
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38),
BITS_WITH_WMASK(767, 0x3fff, 0) |
BITS_WITH_WMASK(2, 0x3, 14));
BITS_WITH_WMASK(2U, 0x3u, 14));
}
static void pm_plls_resume(void)
@ -411,7 +411,7 @@ static void pm_plls_resume(void)
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38),
ddr_data.clk_sel38 |
BITS_WMSK(0x3fff, 0) |
BITS_WMSK(0x3, 14));
BITS_WMSK(0x3u, 14));
/* uart2 */
mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18),
@ -483,7 +483,7 @@ __sramfunc void rk3328_pmic_resume(void)
mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]);
mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]);
mmio_write_32(GRF_BASE + PMIC_SLEEP_REG,
sram_data.pmic_sleep_save | BITS_WMSK(0xffff, 0));
sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0));
/* Resuming volt need a lot of time */
sram_udelay(100);
}

4
plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c
View File

@ -400,7 +400,7 @@ void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 0))
& 0xffff) |
(0xFFFF << 16);
(0xFFFFu << 16);
p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 1))
& 0xffff);
@ -410,7 +410,7 @@ void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 3))
& 0xffff) |
(0xFFFF << 16);
(0xFFFFu << 16);
} else {
ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]);
}

4
plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h
View File

@ -222,7 +222,7 @@
#define DDRPHY0_SRSTN_REQ(n) (((0x1 << 0) << 16) | (n << 0))
/* CRU_DPLL_CON2 */
#define DPLL_STATUS_LOCK (1 << 31)
#define DPLL_STATUS_LOCK (1U << 31)
/* CRU_DPLL_CON3 */
#define DPLL_POWER_DOWN ((0x1 << (1 + 16)) | (0 << 1))
@ -237,7 +237,7 @@
#define DDR_PLL_SRC_MASK 0x13
/* DDR_PCTL_TREFI */
#define DDR_UPD_REF_ENABLE (0X1 << 31)
#define DDR_UPD_REF_ENABLE (0X1u << 31)
uint32_t ddr_get_resume_code_size(void);
uint32_t ddr_get_resume_data_size(void);

2
plat/rockchip/rk3368/drivers/soc/soc.h
View File

@ -50,7 +50,7 @@ enum plls_id {
#define PMUSRAM_S 1
#define STIMER_S_SHIFT 6
#define STIMER_S 1
#define SGRF_SOC_CON7_BITS ((0xffff << 16) | \
#define SGRF_SOC_CON7_BITS ((0xffffu << 16) | \
(PMUSRAM_S << PMUSRAM_S_SHIFT) | \
(STIMER_S << STIMER_S_SHIFT))

98
plat/rockchip/rk3399/drivers/dram/dfs.c
View File

@ -504,7 +504,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
(pdram_timing->tmod << 8) |
pdram_timing->tmrd);
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
(pdram_timing->txsr -
pdram_timing->trcd) << 16);
} else if (timing_config->dram_type == LPDDR4) {
@ -513,7 +513,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
mmio_write_32(CTL_REG(i, 32),
(pdram_timing->tmrd << 8) |
pdram_timing->tmrd);
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
pdram_timing->txsr << 16);
} else {
mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1);
@ -521,7 +521,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
mmio_write_32(CTL_REG(i, 32),
(pdram_timing->tmrd << 8) |
pdram_timing->tmrd);
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
pdram_timing->txsr << 16);
}
mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3);
@ -531,7 +531,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24),
(pdram_timing->cwl << 24));
mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al);
mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16,
(pdram_timing->trc << 24) |
(pdram_timing->trrd << 16));
mmio_write_32(CTL_REG(i, 27),
@ -540,7 +540,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
(pdram_timing->twtr << 8) |
pdram_timing->tras_min);
mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24,
max(4, pdram_timing->trtp) << 24);
mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) |
pdram_timing->tras_max);
@ -560,7 +560,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
((pdram_timing->trefi - 8) << 16) |
pdram_timing->trfc);
mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp);
mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 53), 0xffffu << 16,
pdram_timing->txpdll << 16);
mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24,
pdram_timing->tcscke << 24);
@ -571,7 +571,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
(pdram_timing->tckehcs << 8) |
pdram_timing->tckelcs);
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr);
mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 62), 0xffffu << 16,
(pdram_timing->tckehcmd << 24) |
(pdram_timing->tckelcmd << 16));
mmio_write_32(CTL_REG(i, 63),
@ -601,7 +601,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
pdram_timing->mr[2]);
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff,
pdram_timing->mr[3]);
mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 139), 0xffu << 24,
pdram_timing->mr11 << 24);
mmio_write_32(CTL_REG(i, 147),
(pdram_timing->mr[1] << 16) |
@ -610,20 +610,20 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
pdram_timing->mr[2]);
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff,
pdram_timing->mr[3]);
mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 153), 0xffu << 24,
pdram_timing->mr11 << 24);
if (timing_config->dram_type == LPDDR4) {
mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 140), 0xffffu << 16,
pdram_timing->mr12 << 16);
mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 142), 0xffffu << 16,
pdram_timing->mr14 << 16);
mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 145), 0xffffu << 16,
pdram_timing->mr22 << 16);
mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 154), 0xffffu << 16,
pdram_timing->mr12 << 16);
mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 156), 0xffffu << 16,
pdram_timing->mr14 << 16);
mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 159), 0xffffu << 16,
pdram_timing->mr22 << 16);
}
mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8,
@ -655,7 +655,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
<< 8) | get_rdlat_adj(timing_config->dram_type,
pdram_timing->cl);
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp);
mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 82), 0xffffu << 16,
(4 * pdram_timing->trefi) << 16);
mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff,
@ -748,13 +748,13 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
pdram_timing->tmod + pdram_timing->tzqinit;
mmio_write_32(CTL_REG(i, 9), tmp);
mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 22), 0xffffu << 16,
pdram_timing->tdllk << 16);
mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00,
(pdram_timing->tmod << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
(pdram_timing->txsr -
pdram_timing->trcd) << 16);
} else if (timing_config->dram_type == LPDDR4) {
@ -764,7 +764,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
(pdram_timing->tmrd << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
pdram_timing->txsr << 16);
} else {
mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1);
@ -773,7 +773,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
(pdram_timing->tmrd << 24) |
(pdram_timing->tmrd << 16) |
(pdram_timing->trtp << 8));
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
pdram_timing->txsr << 16);
}
mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3);
@ -796,7 +796,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
pdram_timing->tras_max);
mmio_clrsetbits_32(CTL_REG(i, 36), 0xff,
max(1, pdram_timing->tckesr));
mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24),
mmio_clrsetbits_32(CTL_REG(i, 39), (0xffu << 24),
(pdram_timing->trcd << 24));
mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr);
mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24,
@ -809,7 +809,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
mmio_write_32(CTL_REG(i, 49),
((pdram_timing->trefi - 8) << 16) |
pdram_timing->trfc);
mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 52), 0xffffu << 16,
pdram_timing->txp << 16);
mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff,
pdram_timing->txpdll);
@ -821,7 +821,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
pdram_timing->tcscke);
mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke);
mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr);
mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 64), 0xffffu << 16,
(pdram_timing->tckehcmd << 24) |
(pdram_timing->tckelcmd << 16));
mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) |
@ -831,7 +831,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff,
(pdram_timing->tcmdcke << 8) |
pdram_timing->tcsckeh);
mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24),
mmio_clrsetbits_32(CTL_REG(i, 92), (0xffu << 24),
(pdram_timing->tcksre << 24));
mmio_clrsetbits_32(CTL_REG(i, 93), 0xff,
pdram_timing->tcksrx);
@ -845,18 +845,18 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
pdram_timing->tfc_long);
mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff,
pdram_timing->tvref_long);
mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 134), 0xffffu << 16,
pdram_timing->mr[0] << 16);
mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) |
pdram_timing->mr[1]);
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffffu << 16,
pdram_timing->mr[3] << 16);
mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11);
mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 148), 0xffffu << 16,
pdram_timing->mr[0] << 16);
mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) |
pdram_timing->mr[1]);
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffffu << 16,
pdram_timing->mr[3] << 16);
mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11);
if (timing_config->dram_type == LPDDR4) {
@ -907,7 +907,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff,
(4 * pdram_timing->trefi) & 0xffff);
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffffu << 16,
((2 * pdram_timing->trefi) & 0xffff) << 16);
if ((timing_config->dram_type == LPDDR3) ||
@ -936,12 +936,12 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16,
(tmp & 0x3f) << 16);
mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 275), 0xffu << 24,
(get_pi_tdfi_phy_rdlat(pdram_timing,
timing_config) &
0xff) << 24);
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16,
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffffu << 16,
((2 * pdram_timing->trefi) & 0xffff) << 16);
mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff,
@ -973,7 +973,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
tmp = tmp1 - 2;
}
mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24);
mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24);
/* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */
if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&
@ -1036,7 +1036,7 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
tmp = 2 * pdram_timing->trefi;
mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp);
/* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */
mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16);
mmio_clrsetbits_32(PI_REG(i, 7), 0xffffu << 16, tmp << 16);
/* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */
if (timing_config->dram_type == LPDDR4)
@ -1060,14 +1060,14 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16,
(pdram_timing->cl * 2) << 16);
/* PI_46 PI_TREF_F0:RW:16:16 */
mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 46), 0xffffu << 16,
pdram_timing->trefi << 16);
/* PI_46 PI_TRFC_F0:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc);
/* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */
if (timing_config->dram_type == LPDDR3) {
tmp = get_pi_todtoff_max(pdram_timing, timing_config);
mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 66), 0xffu << 24,
tmp << 24);
}
/* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */
@ -1148,19 +1148,19 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
/* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]);
/* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 140), 0xffffu << 16,
pdram_timing->mr[1] << 16);
/* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]);
/* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]);
/* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 133), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]);
/* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 148), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_156 PI_TFC_F0:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff,
@ -1177,10 +1177,10 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
/* PI_158 PI_TRP_F0:RW:0:8 */
mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp);
/* PI_157 PI_TRTP_F0:RW:24:8 */
mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 157), 0xffu << 24,
pdram_timing->trtp << 24);
/* PI_159 PI_TRAS_MIN_F0:RW:24:8 */
mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 159), 0xffu << 24,
pdram_timing->tras_min << 24);
/* PI_159 PI_TRAS_MAX_F0:RW:0:17 */
tmp = pdram_timing->tras_max * 99 / 100;
@ -1237,7 +1237,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8,
(pdram_timing->cl * 2) << 8);
/* PI_47 PI_TREF_F1:RW:16:16 */
mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 47), 0xffffu << 16,
pdram_timing->trefi << 16);
/* PI_47 PI_TRFC_F1:RW:0:10 */
mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc);
@ -1278,10 +1278,10 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16);
/*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */
tmp = get_pi_rdlat_adj(pdram_timing);
mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24);
mmio_clrsetbits_32(PI_REG(i, 89), 0xffu << 24, tmp << 24);
/* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */
tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24);
mmio_clrsetbits_32(PI_REG(i, 90), 0xffu << 24, tmp << 24);
/* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */
tmp1 = tmp;
if (tmp1 == 0)
@ -1290,7 +1290,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
tmp = tmp1 - 1;
else
tmp = tmp1 - 5;
mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24);
mmio_clrsetbits_32(PI_REG(i, 91), 0xffu << 24, tmp << 24);
/*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */
/* tadr=20ns */
tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
@ -1333,12 +1333,12 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8,
pdram_timing->mr[1] << 8);
/* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 128), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]);
/* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */
mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16,
mmio_clrsetbits_32(PI_REG(i, 143), 0xffffu << 16,
pdram_timing->mr[2] << 16);
/* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */
mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]);
@ -1351,7 +1351,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
/* PI_162 PI_TWTR_F1:RW:0:6 */
mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr);
/* PI_161 PI_TRCD_F1:RW:24:8 */
mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 161), 0xffu << 24,
pdram_timing->trcd << 24);
/* PI_161 PI_TRP_F1:RW:16:8 */
mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16,
@ -1360,7 +1360,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8,
pdram_timing->trtp << 8);
/* PI_163 PI_TRAS_MIN_F1:RW:24:8 */
mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24,
mmio_clrsetbits_32(PI_REG(i, 163), 0xffu << 24,
pdram_timing->tras_min << 24);
/* PI_163 PI_TRAS_MAX_F1:RW:0:17 */
mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff,
@ -1765,7 +1765,7 @@ uint32_t exit_low_power(void)
0x40) {
while (mmio_read_32(CTL_REG(i, 200)) & 0x1)
;
mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24,
mmio_clrsetbits_32(CTL_REG(i, 93), 0xffu << 24,
0x69 << 24);
while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) !=
0x40)

4
plat/rockchip/rk3399/drivers/dram/suspend.c
View File

@ -172,7 +172,7 @@ static __pmusramfunc void override_write_leveling_value(uint32_t ch)
mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16,
1 << 16);
mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)),
0xffff << 16,
0xffffu << 16,
0x200 << 16);
}
@ -656,7 +656,7 @@ __pmusramfunc static void pmusram_restore_pll(int pll_id, uint32_t *src)
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
(1 << 31)) == 0x0)
(1U << 31)) == 0x0)
;
}

4
plat/rockchip/rk3399/drivers/pmu/m0_ctl.c
View File

@ -45,10 +45,10 @@ void m0_configure_execute_addr(uintptr_t addr)
/* set the execute address for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
BITS_WITH_WMASK((addr >> 12) & 0xffff,
0xffff, 0));
0xffffu, 0));
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
BITS_WITH_WMASK((addr >> 28) & 0xf,
0xf, 0));
0xfu, 0));
}
void m0_start(void)