Cortex-A76: Optimize CVE_2018_3639 workaround
Switched from a static check to a runtime assert to make sure a workaround is implemented for CVE_2018_3639. This allows platforms that know they have the SSBS hardware workaround in the CPU to compile out code under DYNAMIC_WORKAROUND_CVE_2018_3639. The gain in memory size without the dynamic workaround is 4KB in bl31. Change-Id: I61bb7d87c59964b0c7faac5d6bc7fc5c4651cbf3 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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@ -13,13 +13,10 @@
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#include <plat_macros.S>
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#include <services/arm_arch_svc.h>
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#if !DYNAMIC_WORKAROUND_CVE_2018_3639
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#error Cortex A76 requires DYNAMIC_WORKAROUND_CVE_2018_3639=1
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#endif
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#define ESR_EL3_A64_SMC0 0x5e000000
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#define ESR_EL3_A32_SMC0 0x4e000000
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#if DYNAMIC_WORKAROUND_CVE_2018_3639
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/*
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* This macro applies the mitigation for CVE-2018-3639.
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* It implements a fast path where `SMCCC_ARCH_WORKAROUND_2`
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@ -188,6 +185,7 @@ vector_entry cortex_a76_serror_aarch32
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apply_cve_2018_3639_wa _is_sync_exception=0 _esr_el3_val=ESR_EL3_A32_SMC0
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b serror_aarch32
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end_vector_entry cortex_a76_serror_aarch32
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#endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
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/* --------------------------------------------------
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* Errata Workaround for Cortex A76 Errata #1073348.
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@ -320,8 +318,12 @@ func cortex_a76_reset_func
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mrs x0, id_aa64pfr1_el1
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lsr x0, x0, #ID_AA64PFR1_EL1_SSBS_SHIFT
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and x0, x0, #ID_AA64PFR1_EL1_SSBS_MASK
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#if !DYNAMIC_WORKAROUND_CVE_2018_3639 && ENABLE_ASSERTIONS
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cmp x0, 0
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ASM_ASSERT(ne)
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#endif
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#if DYNAMIC_WORKAROUND_CVE_2018_3639
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cbnz x0, 1f
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mrs x0, CORTEX_A76_CPUACTLR2_EL1
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orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
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msr CORTEX_A76_CPUACTLR2_EL1, x0
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@ -336,10 +338,11 @@ func cortex_a76_reset_func
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adr x0, cortex_a76_wa_cve_2018_3639_a76_vbar
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msr vbar_el3, x0
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isb
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#endif
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#endif /* IMAGE_BL31 */
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1:
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#endif
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#endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
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#endif /* WORKAROUND_CVE_2018_3639 */
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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