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rockchip: px30: move secure init to separate file 

Similar to others like rk3399 and rk3288 move the secure init to a
separate file to unclutter the soc init a bit.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691
This commit is contained in:
Heiko Stuebner 2019-10-09 12:15:56 +02:00
parent 7f0b2e78e0
commit d2483afac9
6 changed files with 137 additions and 114 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
plat/rockchip/px30/drivers/pmu/pmu.c
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@ -22,6 +22,7 @@
#include <plat_private.h>
#include <pmu.h>
#include <px30_def.h>
#include <secure.h>
#include <soc.h>
DEFINE_BAKERY_LOCK(rockchip_pd_lock);

68
plat/rockchip/px30/drivers/secure/secure.c Normal file
View File

@ -0,0 +1,68 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <ddr_parameter.h>
#include <secure.h>
#include <px30_def.h>
void secure_timer_init(void)
{
mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
TIMER_DIS);
mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
/* auto reload & enable the timer */
mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
TIMER_EN | TIMER_FMODE);
}
void sgrf_init(void)
{
uint32_t i, val;
struct param_ddr_usage usg;
/* general secure regions */
usg = ddr_region_usage_parse(DDR_PARAM_BASE,
PLAT_MAX_DDR_CAPACITY_MB);
for (i = 0; i < usg.s_nr; i++) {
/* enable secure */
val = mmio_read_32(FIREWALL_DDR_BASE +
FIREWALL_DDR_FW_DDR_CON_REG);
val |= BIT(7 - i);
mmio_write_32(FIREWALL_DDR_BASE +
FIREWALL_DDR_FW_DDR_CON_REG, val);
/* map top and base */
mmio_write_32(FIREWALL_DDR_BASE +
FIREWALL_DDR_FW_DDR_RGN(7 - i),
RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
}
/* set ddr rgn0_top and rga0_top as 0 */
mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
/* set all slave ip into no-secure, except stimer */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
/* set master crypto to no-secure, dcf to secure */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
/* set DMAC into no-secure */
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
/* soft reset dma before use */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
udelay(5);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
}

65
plat/rockchip/px30/drivers/secure/secure.h Normal file
View File

@ -0,0 +1,65 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SECURE_H
#define SECURE_H
/***************************************************************************
* SGRF
***************************************************************************/
#define SGRF_SOC_CON(i) ((i) * 0x4)
#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4)
#define SGRF_MST_S_ALL_NS 0xffffffff
#define SGRF_SLV_S_ALL_NS 0xffff0000
#define DMA_IRQ_BOOT_NS 0xffffffff
#define DMA_PERI_CH_NS_15_0 0xffffffff
#define DMA_PERI_CH_NS_19_16 0x000f000f
#define DMA_MANAGER_BOOT_NS 0x00010001
#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
/***************************************************************************
* DDR FIREWALL
***************************************************************************/
#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
#define FIREWALL_DDR_FW_DDR_MST_NUM 6
#define PLAT_MAX_DDR_CAPACITY_MB 4096
#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
/**************************************************
* secure timer
**************************************************/
/* chanal0~5 */
#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
#define TIMER_LOAD_COUNT0 0x0
#define TIMER_LOAD_COUNT1 0x4
#define TIMER_CUR_VALUE0 0x8
#define TIMER_CUR_VALUE1 0xc
#define TIMER_CONTROL_REG 0x10
#define TIMER_INTSTATUS 0x18
#define TIMER_DIS 0x0
#define TIMER_EN 0x1
#define TIMER_FMODE (0x0 << 1)
#define TIMER_RMODE (0x1 << 1)
#define TIMER_LOAD_COUNT0_MSK (0xffffffff)
#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000)
void secure_timer_init(void);
void sgrf_init(void);
#endif /* SECURE_H */

61
plat/rockchip/px30/drivers/soc/soc.c
View File

@ -12,10 +12,10 @@
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <ddr_parameter.h>
#include <platform_def.h>
#include <pmu.h>
#include <px30_def.h>
#include <secure.h>
#include <soc.h>
#include <rockchip_sip_svc.h>
@ -83,65 +83,6 @@ void clk_gate_con_disable(void)
0xffff0000);
}
void secure_timer_init(void)
{
mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
TIMER_DIS);
mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
/* auto reload & enable the timer */
mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
TIMER_EN | TIMER_FMODE);
}
static void sgrf_init(void)
{
uint32_t i, val;
struct param_ddr_usage usg;
/* general secure regions */
usg = ddr_region_usage_parse(DDR_PARAM_BASE,
PLAT_MAX_DDR_CAPACITY_MB);
for (i = 0; i < usg.s_nr; i++) {
/* enable secure */
val = mmio_read_32(FIREWALL_DDR_BASE +
FIREWALL_DDR_FW_DDR_CON_REG);
val |= BIT(7 - i);
mmio_write_32(FIREWALL_DDR_BASE +
FIREWALL_DDR_FW_DDR_CON_REG, val);
/* map top and base */
mmio_write_32(FIREWALL_DDR_BASE +
FIREWALL_DDR_FW_DDR_RGN(7 - i),
RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
}
/* set ddr rgn0_top and rga0_top as 0 */
mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
/* set all slave ip into no-secure, except stimer */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
/* set master crypto to no-secure, dcf to secure */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
/* set DMAC into no-secure */
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
/* soft reset dma before use */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
udelay(5);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
}
static void soc_reset_config_all(void)
{
uint32_t tmp;

54
plat/rockchip/px30/drivers/soc/soc.h
View File

@ -28,21 +28,6 @@ enum pll_mode {
DEEP_SLOW_MODE,
};
/***************************************************************************
* SGRF
***************************************************************************/
#define SGRF_SOC_CON(i) ((i) * 0x4)
#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4)
#define SGRF_MST_S_ALL_NS 0xffffffff
#define SGRF_SLV_S_ALL_NS 0xffff0000
#define DMA_IRQ_BOOT_NS 0xffffffff
#define DMA_PERI_CH_NS_15_0 0xffffffff
#define DMA_PERI_CH_NS_19_16 0x000f000f
#define DMA_MANAGER_BOOT_NS 0x00010001
#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
/***************************************************************************
* GRF
***************************************************************************/
@ -60,18 +45,6 @@ enum pll_mode {
#define GRF_SOC_CON2_NSWDT_RST_EN 12
/***************************************************************************
* DDR FIREWALL
***************************************************************************/
#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
#define FIREWALL_DDR_FW_DDR_MST_NUM 6
#define PLAT_MAX_DDR_CAPACITY_MB 4096
#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
/***************************************************************************
* cru
***************************************************************************/
@ -136,37 +109,10 @@ enum pll_mode {
#define GPIO_INT_STATUS 0x40
#define GPIO_NUMS 4
/**************************************************
* secure timer
**************************************************/
/* chanal0~5 */
#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
#define TIMER_LOAD_COUNT0 0x0
#define TIMER_LOAD_COUNT1 0x4
#define TIMER_CUR_VALUE0 0x8
#define TIMER_CUR_VALUE1 0xc
#define TIMER_CONTROL_REG 0x10
#define TIMER_INTSTATUS 0x18
#define TIMER_DIS 0x0
#define TIMER_EN 0x1
#define TIMER_FMODE (0x0 << 1)
#define TIMER_RMODE (0x1 << 1)
#define TIMER_LOAD_COUNT0_MSK (0xffffffff)
#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000)
void clk_gate_con_save(uint32_t *clkgt_save);
void clk_gate_con_restore(uint32_t *clkgt_save);
void clk_gate_con_disable(void);
void secure_timer_init(void);
void secure_timer_disable(void);
void px30_soc_reset_config(void);
#endif /* __SOC_H__ */

2
plat/rockchip/px30/platform.mk
View File

@ -20,6 +20,7 @@ PLAT_INCLUDES := -Idrivers/arm/gic/common/ \
-I${RK_PLAT_COMMON}/pmusram \
-I${RK_PLAT_SOC}/ \
-I${RK_PLAT_SOC}/drivers/pmu/ \
-I${RK_PLAT_SOC}/drivers/secure/ \
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/include/
@ -52,6 +53,7 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/secure/secure.c \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/plat_sip_calls.c