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Merge changes from topic "tegra-downstream-08282020" into integration 

* changes:
  Tegra: platform specific BL31_SIZE
  Tegra186: sanity check power state type
  Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
  Tegra: add platform specific 'runtime_setup' handler
  Tegra: remove ENABLE_SVE_FOR_NS = 0
  lib: cpus: denver: add MIDR PN9 variant
  cpus: denver: introduce macro to declare cpu_ops
This commit is contained in:
Varun Wadekar 2020-08-31 22:46:37 +00:00 committed by TrustedFirmware Code Review
parent ddf287000b 5a22eb421d
commit d35403feab
16 changed files with 166 additions and 93 deletions
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1
include/lib/cpus/aarch64/denver.h
View File

@ -17,6 +17,7 @@
#define DENVER_MIDR_PN6 U(0x4E0F0060)
#define DENVER_MIDR_PN7 U(0x4E0F0070)
#define DENVER_MIDR_PN8 U(0x4E0F0080)
#define DENVER_MIDR_PN9 U(0x4E0F0090)
/* Implementer code in the MIDR register */
#define DENVER_IMPL U(0x4E)

80
lib/cpus/aarch64/denver.S
View File

@ -353,65 +353,23 @@ func denver_cpu_reg_dump
ret
endfunc denver_cpu_reg_dump
declare_cpu_ops_wa denver, DENVER_MIDR_PN0, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
/* macro to declare cpu_ops for Denver SKUs */
.macro denver_cpu_ops_wa midr
declare_cpu_ops_wa denver, \midr, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
.endm
declare_cpu_ops_wa denver, DENVER_MIDR_PN1, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
declare_cpu_ops_wa denver, DENVER_MIDR_PN2, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
declare_cpu_ops_wa denver, DENVER_MIDR_PN3, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
declare_cpu_ops_wa denver, DENVER_MIDR_PN4, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
declare_cpu_ops_wa denver, DENVER_MIDR_PN5, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
declare_cpu_ops_wa denver, DENVER_MIDR_PN6, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
declare_cpu_ops_wa denver, DENVER_MIDR_PN7, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
declare_cpu_ops_wa denver, DENVER_MIDR_PN8, \
denver_reset_func, \
check_errata_cve_2017_5715, \
CPU_NO_EXTRA2_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
denver_cpu_ops_wa DENVER_MIDR_PN0
denver_cpu_ops_wa DENVER_MIDR_PN1
denver_cpu_ops_wa DENVER_MIDR_PN2
denver_cpu_ops_wa DENVER_MIDR_PN3
denver_cpu_ops_wa DENVER_MIDR_PN4
denver_cpu_ops_wa DENVER_MIDR_PN5
denver_cpu_ops_wa DENVER_MIDR_PN6
denver_cpu_ops_wa DENVER_MIDR_PN7
denver_cpu_ops_wa DENVER_MIDR_PN8
denver_cpu_ops_wa DENVER_MIDR_PN9

26
plat/nvidia/tegra/common/tegra_bl31_setup.c
View File

@ -253,31 +253,9 @@ void bl31_platform_setup(void)
void bl31_plat_runtime_setup(void)
{
/*
* During cold boot, it is observed that the arbitration
* bit is set in the Memory controller leading to false
* error interrupts in the non-secure world. To avoid
* this, clean the interrupt status register before
* booting into the non-secure world
* Platform specific runtime setup
*/
tegra_memctrl_clear_pending_interrupts();
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
* do not have a direct path to the IRAM, the MC implements AHB
* redirection during boot to allow path to IRAM. In this mode
* accesses to a programmed memory address aperture are directed
* to the AHB bus, allowing access to the IRAM. This mode must be
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
#if defined(TEGRA_SMMU0_BASE)
/*
* Verify the integrity of the previously configured SMMU(s) settings
*/
tegra_smmu_verify();
#endif
plat_runtime_setup();
/*
* Add final timestamp before exiting BL31.

6
plat/nvidia/tegra/common/tegra_delay_timer.c
View File

@ -22,11 +22,9 @@ static uint32_t tegra_timer_get_value(void)
/*
* Generic delay timer implementation expects the timer to be a down
* counter. We apply bitwise NOT operator to the tick values returned
* by read_cntps_tval_el1() to simulate the down counter. The value is
* clipped from 64 to 32 bits.
* counter. The value is clipped from 64 to 32 bits.
*/
return (uint32_t)(~read_cntps_tval_el1());
return (uint32_t)(read_cntps_tval_el1());
}
/*

1
plat/nvidia/tegra/include/platform_def.h
View File

@ -66,7 +66,6 @@
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
#define BL31_SIZE U(0x40000)
#define BL31_BASE TZDRAM_BASE
#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)

5
plat/nvidia/tegra/include/t132/tegra_def.h
View File

@ -10,6 +10,11 @@
#include <lib/utils_def.h>
/*******************************************************************************
* Platform BL31 specific defines.
******************************************************************************/
#define BL31_SIZE U(0x40000)
/*******************************************************************************
* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
* call as the `state-id` field in the 'power state' parameter.

5
plat/nvidia/tegra/include/t186/tegra_def.h
View File

@ -10,6 +10,11 @@
#include <lib/utils_def.h>
/*******************************************************************************
* Platform BL31 specific defines.
******************************************************************************/
#define BL31_SIZE U(0x40000)
/*******************************************************************************
* MCE apertures used by the ARI interface
*

5
plat/nvidia/tegra/include/t194/tegra_def.h
View File

@ -9,6 +9,11 @@
#include <lib/utils_def.h>
/*******************************************************************************
* Platform BL31 specific defines.
******************************************************************************/
#define BL31_SIZE U(0x40000)
/*******************************************************************************
* Chip specific cluster and cpu numbers
******************************************************************************/

5
plat/nvidia/tegra/include/t210/tegra_def.h
View File

@ -10,6 +10,11 @@
#include <lib/utils_def.h>
/*******************************************************************************
* Platform BL31 specific defines.
******************************************************************************/
#define BL31_SIZE U(0x40000)
/*******************************************************************************
* Power down state IDs
******************************************************************************/

1
plat/nvidia/tegra/include/tegra_private.h
View File

@ -87,6 +87,7 @@ void plat_early_platform_setup(void);
void plat_late_platform_setup(void);
void plat_relocate_bl32_image(const image_info_t *bl32_img_info);
bool plat_supports_system_suspend(void);
void plat_runtime_setup(void);
/* Declarations for plat_secondary.c */
void plat_secondary_setup(void);

3
plat/nvidia/tegra/platform.mk
View File

@ -33,9 +33,6 @@ SEPARATE_CODE_AND_RODATA := 1
# do not use coherent memory
USE_COHERENT_MEM := 0
# do not enable SVE
ENABLE_SVE_FOR_NS := 0
# enable D-cache early during CPU warmboot
WARMBOOT_ENABLE_DCACHE_EARLY := 1

26
plat/nvidia/tegra/soc/t132/plat_setup.c
View File

@ -173,3 +173,29 @@ bool plat_supports_system_suspend(void)
{
return true;
}
/*******************************************************************************
* Platform specific runtime setup.
******************************************************************************/
void plat_runtime_setup(void)
{
/*
* During cold boot, it is observed that the arbitration
* bit is set in the Memory controller leading to false
* error interrupts in the non-secure world. To avoid
* this, clean the interrupt status register before
* booting into the non-secure world
*/
tegra_memctrl_clear_pending_interrupts();
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
* do not have a direct path to the IRAM, the MC implements AHB
* redirection during boot to allow path to IRAM. In this mode
* accesses to a programmed memory address aperture are directed
* to the AHB bus, allowing access to the IRAM. This mode must be
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
}

5
plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
View File

@ -72,6 +72,11 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
case PSTATE_ID_CORE_IDLE:
case PSTATE_ID_CORE_POWERDN:
if (psci_get_pstate_type(power_state) != PSTATE_TYPE_POWERDOWN) {
ret = PSCI_E_INVALID_PARAMS;
break;
}
/* Core powerdown request */
req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id;
req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;

32
plat/nvidia/tegra/soc/t186/plat_setup.c
View File

@ -27,6 +27,7 @@
#include <mce.h>
#include <memctrl.h>
#include <smmu.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
@ -363,3 +364,34 @@ bool plat_supports_system_suspend(void)
{
return true;
}
/*******************************************************************************
* Platform specific runtime setup.
******************************************************************************/
void plat_runtime_setup(void)
{
/*
* During cold boot, it is observed that the arbitration
* bit is set in the Memory controller leading to false
* error interrupts in the non-secure world. To avoid
* this, clean the interrupt status register before
* booting into the non-secure world
*/
tegra_memctrl_clear_pending_interrupts();
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
* do not have a direct path to the IRAM, the MC implements AHB
* redirection during boot to allow path to IRAM. In this mode
* accesses to a programmed memory address aperture are directed
* to the AHB bus, allowing access to the IRAM. This mode must be
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
/*
* Verify the integrity of the previously configured SMMU(s)
* settings
*/
tegra_smmu_verify();
}

33
plat/nvidia/tegra/soc/t194/plat_setup.c
View File

@ -20,7 +20,9 @@
#include <bl31/interrupt_mgmt.h>
#include <mce.h>
#include <mce_private.h>
#include <memctrl.h>
#include <plat/common/platform.h>
#include <smmu.h>
#include <spe.h>
#include <tegra_def.h>
#include <tegra_platform.h>
@ -414,3 +416,34 @@ bool plat_supports_system_suspend(void)
{
return true;
}
/*******************************************************************************
* Platform specific runtime setup.
******************************************************************************/
void plat_runtime_setup(void)
{
/*
* During cold boot, it is observed that the arbitration
* bit is set in the Memory controller leading to false
* error interrupts in the non-secure world. To avoid
* this, clean the interrupt status register before
* booting into the non-secure world
*/
tegra_memctrl_clear_pending_interrupts();
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
* do not have a direct path to the IRAM, the MC implements AHB
* redirection during boot to allow path to IRAM. In this mode
* accesses to a programmed memory address aperture are directed
* to the AHB bus, allowing access to the IRAM. This mode must be
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
/*
* Verify the integrity of the previously configured SMMU(s) settings
*/
tegra_smmu_verify();
}

25
plat/nvidia/tegra/soc/t210/plat_setup.c
View File

@ -291,3 +291,28 @@ bool plat_supports_system_suspend(void)
return false;
}
}
/*******************************************************************************
* Platform specific runtime setup.
******************************************************************************/
void plat_runtime_setup(void)
{
/*
* During cold boot, it is observed that the arbitration
* bit is set in the Memory controller leading to false
* error interrupts in the non-secure world. To avoid
* this, clean the interrupt status register before
* booting into the non-secure world
*/
tegra_memctrl_clear_pending_interrupts();
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
* do not have a direct path to the IRAM, the MC implements AHB
* redirection during boot to allow path to IRAM. In this mode
* accesses to a programmed memory address aperture are directed
* to the AHB bus, allowing access to the IRAM. This mode must be
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
}