Add CPU specific crash reporting handlers
This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register state to the CPU specific operations framework. The contents of CPUECTLR_EL1 are dumped currently. Change-Id: I63d3dbfc4ac52fef5e25a8cf6b937c6f0975c8ab
This commit is contained in:
Soby Mathew
Dan Handley
parent
add403514d
commit
d3f70af6e0
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@ -52,9 +52,6 @@
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print_spacer:
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.asciz " =\t\t0x"
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cpu_ectlr_reg:
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.asciz "cpuectlr_el1 =\t\t0x"
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gp_regs:
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.asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",\
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@ -337,21 +334,9 @@ func do_crash_reporting
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mrs x10, sp_el0
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bl str_in_crash_buf_print
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/* Print the CPUECTLR_EL1 reg */
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mrs x0, midr_el1
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lsr x0, x0, #MIDR_PN_SHIFT
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and x0, x0, #MIDR_PN_MASK
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cmp x0, #MIDR_PN_A57
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b.eq 1f
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cmp x0, #MIDR_PN_A53
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b.ne 2f
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1:
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adr x4, cpu_ectlr_reg
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bl asm_print_str
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mrs x4, CPUECTLR_EL1
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bl asm_print_hex
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bl print_newline
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2:
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/* Get the cpu specific registers to report */
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bl do_cpu_reg_dump
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bl str_in_crash_buf_print
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/* Print the gic registers */
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plat_print_gic_regs
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@ -39,9 +39,6 @@
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#define MIDR_IMPL_SHIFT 0x18
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#define MIDR_PN_MASK 0xfff
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#define MIDR_PN_SHIFT 0x4
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#define MIDR_PN_AEM 0xd0f
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#define MIDR_PN_A57 0xd07
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#define MIDR_PN_A53 0xd03
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/*******************************************************************************
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* MPIDR macros
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@ -76,11 +73,6 @@
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#define ICC_CTLR_EL3 S3_6_C12_C12_4
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#define ICC_PMR_EL1 S3_0_C4_C6_0
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/*******************************************************************************
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* Implementation defined sysreg encodings
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******************************************************************************/
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#define CPUECTLR_EL1 S3_1_C15_C2_1
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/*******************************************************************************
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* Generic timer memory mapped registers & offsets
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******************************************************************************/
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@ -37,6 +37,8 @@
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
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#define CPUECTLR_SMP_BIT (1 << 6)
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#endif /* __CORTEX_A53_H__ */
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@ -37,6 +37,8 @@
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
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#define CPUECTLR_SMP_BIT (1 << 6)
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#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
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#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
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@ -50,6 +50,10 @@ CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
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CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
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.space 8
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#endif
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#if (IMAGE_BL31 && CRASH_REPORTING)
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CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
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.space 8
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#endif
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CPU_OPS_SIZE = .
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/*
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@ -71,5 +75,8 @@ CPU_OPS_SIZE = .
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#if IMAGE_BL31
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.quad \_name\()_core_pwr_dwn
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.quad \_name\()_cluster_pwr_dwn
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#endif
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#if (IMAGE_BL31 && CRASH_REPORTING)
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.quad \_name\()_cpu_reg_dump
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#endif
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.endm
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@ -68,6 +68,19 @@ func aem_generic_cluster_pwr_dwn
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mov x0, #DCCISW
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b dcsw_op_all
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/* ---------------------------------------------
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* This function provides cpu specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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func aem_generic_cpu_reg_dump
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mov x6, #0 /* no registers to report */
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ret
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/* cpu_ops for Base AEM FVP */
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declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1
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@ -119,4 +119,22 @@ func cortex_a53_cluster_pwr_dwn
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mov x30, x18
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b cortex_a53_disable_smp
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/* ---------------------------------------------
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* This function provides cortex_a53 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a53_regs, "aS"
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cortex_a53_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a53_cpu_reg_dump
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adr x6, cortex_a53_regs
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mrs x8, CPUECTLR_EL1
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ret
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR
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@ -167,4 +167,23 @@ func cortex_a57_cluster_pwr_dwn
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mov x30, x18
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b cortex_a57_disable_ext_debug
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/* ---------------------------------------------
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* This function provides cortex_a57 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a57_regs, "aS"
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cortex_a57_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a57_cpu_reg_dump
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adr x6, cortex_a57_regs
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mrs x8, CPUECTLR_EL1
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ret
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declare_cpu_ops cortex_a57, CORTEX_A57_MIDR
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@ -125,6 +125,30 @@ func init_cpu_ops
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ret
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#endif /* IMAGE_BL31 */
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#if IMAGE_BL31 && CRASH_REPORTING
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/*
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* The cpu specific registers which need to be reported in a crash
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* are reported via cpu_ops cpu_reg_dump function. After a matching
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* cpu_ops structure entry is found, the correponding cpu_reg_dump
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* in the cpu_ops is invoked.
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*/
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.globl do_cpu_reg_dump
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func do_cpu_reg_dump
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mov x16, x30
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/* Get the matching cpu_ops pointer */
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bl get_cpu_ops_ptr
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cbz x0, 1f
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/* Get the cpu_ops cpu_reg_dump */
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ldr x2, [x0, #CPU_REG_DUMP]
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cbz x2, 1f
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blr x2
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1:
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mov x30, x16
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ret
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#endif
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/*
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* The below function returns the cpu_ops structure matching the
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* midr of the core. It reads the MIDR_EL1 and finds the matching
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