NXP: Driver for NXP Security Monitor
NXP Security Monitor IP provides hardware anchored - current security state of the SoC. - Tamper detect etc. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I8ff809fe2f3fd013844ab3d4a8733f53c2b06c81
This commit is contained in:
Pankaj Gupta
parent
3979c6d924
commit
d8e9799921
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#
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# Copyright 2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifeq (${ADD_SNVS},)
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ADD_SNVS := 1
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SNVS_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/sec_mon
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PLAT_INCLUDES += -I$(SNVS_DRIVERS_PATH)
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SNVS_SOURCES += $(SNVS_DRIVERS_PATH)/snvs.c
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ifeq (${BL_COMM_SNVS_NEEDED},yes)
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BL_COMMON_SOURCES += ${SNVS_SOURCES}
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else
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ifeq (${BL2_SNVS_NEEDED},yes)
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BL2_SOURCES += ${SNVS_SOURCES}
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endif
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ifeq (${BL31_SNVS_NEEDED},yes)
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BL31_SOURCES += ${SNVS_SOURCES}
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endif
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endif
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endif
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <snvs.h>
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static uintptr_t g_nxp_snvs_addr;
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void snvs_init(uintptr_t nxp_snvs_addr)
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{
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g_nxp_snvs_addr = nxp_snvs_addr;
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}
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uint32_t get_snvs_state(void)
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{
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struct snvs_regs *snvs = (struct snvs_regs *) (g_nxp_snvs_addr);
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return (snvs_read32(&snvs->hp_stat) & HPSTS_MASK_SSM_ST);
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}
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static uint32_t do_snvs_state_transition(uint32_t state_transtion_bit,
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uint32_t target_state)
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{
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struct snvs_regs *snvs = (struct snvs_regs *) (g_nxp_snvs_addr);
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uint32_t sts = get_snvs_state();
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uint32_t fetch_cnt = 16U;
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uint32_t val = snvs_read32(&snvs->hp_com) | state_transtion_bit;
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snvs_write32(&snvs->hp_com, val);
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/* polling loop till SNVS is in target state */
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do {
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sts = get_snvs_state();
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} while ((sts != target_state) && ((--fetch_cnt) != 0));
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return sts;
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}
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void transition_snvs_non_secure(void)
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{
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struct snvs_regs *snvs = (struct snvs_regs *) (g_nxp_snvs_addr);
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uint32_t sts = get_snvs_state();
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switch (sts) {
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/* If initial state is check or Non-Secure, then
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* set the Software Security Violation Bit and
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* transition to Non-Secure State.
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*/
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case HPSTS_CHECK_SSM_ST:
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sts = do_snvs_state_transition(HPCOM_SW_SV, HPSTS_NON_SECURE_SSM_ST);
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break;
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/* If initial state is Trusted, Secure or Soft-Fail, then
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* first set the Software Security Violation Bit and
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* transition to Soft-Fail State.
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*/
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case HPSTS_TRUST_SSM_ST:
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case HPSTS_SECURE_SSM_ST:
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case HPSTS_SOFT_FAIL_SSM_ST:
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sts = do_snvs_state_transition(HPCOM_SW_SV, HPSTS_NON_SECURE_SSM_ST);
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/* If SSM Soft Fail to Non-Secure State Transition
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* Disable is not set, then set SSM_ST bit and
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* transition to Non-Secure State.
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*/
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if ((snvs_read32(&snvs->hp_com) & HPCOM_SSM_SFNS_DIS) == 0) {
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sts = do_snvs_state_transition(HPCOM_SSM_ST, HPSTS_NON_SECURE_SSM_ST);
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}
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break;
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default:
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break;
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}
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}
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void transition_snvs_soft_fail(void)
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{
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do_snvs_state_transition(HPCOM_SW_FSV, HPSTS_SOFT_FAIL_SSM_ST);
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}
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uint32_t transition_snvs_trusted(void)
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{
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struct snvs_regs *snvs = (struct snvs_regs *) (g_nxp_snvs_addr);
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uint32_t sts = get_snvs_state();
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switch (sts) {
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/* If initial state is check, set the SSM_ST bit to
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* change the state to trusted.
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*/
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case HPSTS_CHECK_SSM_ST:
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sts = do_snvs_state_transition(HPCOM_SSM_ST, HPSTS_TRUST_SSM_ST);
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break;
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/* If SSM Secure to Trusted State Transition Disable
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* is not set, then set SSM_ST bit and
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* transition to Trusted State.
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*/
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case HPSTS_SECURE_SSM_ST:
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if ((snvs_read32(&snvs->hp_com) & HPCOM_SSM_ST_DIS) == 0) {
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sts = do_snvs_state_transition(HPCOM_SSM_ST, HPSTS_TRUST_SSM_ST);
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}
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break;
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/* If initial state is Soft-Fail or Non-Secure, then
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* transition to Trusted is not Possible.
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*/
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default:
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break;
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}
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return sts;
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}
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uint32_t transition_snvs_secure(void)
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{
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uint32_t sts = get_snvs_state();
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if (sts == HPSTS_SECURE_SSM_ST) {
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return sts;
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}
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if (sts != HPSTS_TRUST_SSM_ST) {
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sts = transition_snvs_trusted();
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if (sts != HPSTS_TRUST_SSM_ST) {
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return sts;
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}
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}
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sts = do_snvs_state_transition(HPCOM_SSM_ST, HPSTS_TRUST_SSM_ST);
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return sts;
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}
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void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val)
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{
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if (flag_val) {
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snvs_write32(g_nxp_snvs_addr + offset,
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(snvs_read32(g_nxp_snvs_addr + offset))
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| (1 << bit_pos));
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} else {
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snvs_write32(g_nxp_snvs_addr + offset,
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(snvs_read32(g_nxp_snvs_addr + offset))
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& ~(1 << bit_pos));
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}
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}
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uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos)
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{
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return (snvs_read32(g_nxp_snvs_addr + offset) & (1 << bit_pos));
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}
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void snvs_disable_zeroize_lp_gpr(void)
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{
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snvs_write_lp_gpr_bit(NXP_LPCR_OFFSET,
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NXP_GPR_Z_DIS_BIT,
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true);
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}
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#if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB)
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void snvs_write_app_data_bit(uint32_t bit_pos)
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{
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snvs_write_lp_gpr_bit(NXP_APP_DATA_LP_GPR_OFFSET,
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bit_pos,
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true);
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}
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uint32_t snvs_read_app_data(void)
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{
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return snvs_read32(g_nxp_snvs_addr + NXP_APP_DATA_LP_GPR_OFFSET);
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}
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uint32_t snvs_read_app_data_bit(uint32_t bit_pos)
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{
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uint8_t ret = snvs_read_lp_gpr_bit(NXP_APP_DATA_LP_GPR_OFFSET, bit_pos);
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return ((ret != 0U) ? 1U : 0U);
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}
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void snvs_clear_app_data(void)
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{
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snvs_write32(g_nxp_snvs_addr + NXP_APP_DATA_LP_GPR_OFFSET, 0x0);
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}
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#endif
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SNVS_H
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#define SNVS_H
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#ifndef __ASSEMBLER__
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#include <endian.h>
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#include <stdbool.h>
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#include <lib/mmio.h>
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struct snvs_regs {
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uint32_t reserved1;
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uint32_t hp_com; /* 0x04 SNVS_HP Command Register */
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uint32_t reserved2[3];
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uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */
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};
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#ifdef NXP_SNVS_BE
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#define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
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#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v)))
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#elif defined(NXP_SNVS_LE)
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#define snvs_read32(a) mmio_read_32((uintptr_t)(a))
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#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
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#else
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#error Please define CCSR SNVS register endianness
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#endif
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void snvs_init(uintptr_t nxp_snvs_addr);
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uint32_t get_snvs_state(void);
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void transition_snvs_non_secure(void);
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void transition_snvs_soft_fail(void);
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uint32_t transition_snvs_trusted(void);
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uint32_t transition_snvs_secure(void);
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uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos);
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void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val);
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void snvs_disable_zeroize_lp_gpr(void);
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#if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB)
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uint32_t snvs_read_app_data(void);
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uint32_t snvs_read_app_data_bit(uint32_t bit_pos);
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void snvs_clear_app_data(void);
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void snvs_write_app_data_bit(uint32_t bit_pos);
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#endif
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#endif /* __ASSEMBLER__ */
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/* SSM_ST field in SNVS status reg */
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#define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */
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#define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */
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#define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */
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#define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */
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#define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */
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#define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */
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/* SNVS register bits */
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#define HPCOM_SW_SV 0x100 /* Security Violation bit */
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#define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */
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#define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */
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#define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
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#define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
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#define NXP_LP_GPR0_OFFSET 0x90
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#define NXP_LPCR_OFFSET 0x38
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#define NXP_GPR_Z_DIS_BIT 24
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#ifdef NXP_COINED_BB
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#ifndef NXP_APP_DATA_LP_GPR_OFFSET
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#define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET
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#endif
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#define NXP_LPGPR_ZEROTH_BIT 0
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#endif /* NXP_COINED_BB */
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#endif /* SNVS_H */
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