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Merge "fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif" into integration

This commit is contained in:
Manish Pandey 2021-07-28 11:29:32 +02:00 committed by TrustedFirmware Code Review
parent 7bfec3adf3 5a5e0aac39
commit d985cb743b
1 changed files with 4 additions and 0 deletions
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4
drivers/arm/gic/v3/gicv3_main.c
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@ -332,6 +332,8 @@ void gicv3_cpuif_enable(unsigned int proc_num)
write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
IGRPEN1_EL3_ENABLE_G1S_BIT);
isb();
/* Add DSB to ensure visibility of System register writes */
dsb();
}
/*******************************************************************************
@ -363,6 +365,8 @@ void gicv3_cpuif_disable(unsigned int proc_num)
/* Synchronise accesses to group enable registers */
isb();
/* Add DSB to ensure visibility of System register writes */
dsb();
/* Mark the connected core as asleep */
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];