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Workaround for Cortex A76 erratum 1800710 

Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core.  The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.

This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493
This commit is contained in:
johpow01 2020-06-02 15:02:28 -05:00
parent d7b08e6904
commit dcbfbcb5de
4 changed files with 47 additions and 0 deletions
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3
docs/design/cpu-specific-build-macros.rst
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@ -230,6 +230,9 @@ For Cortex-A76, the following errata build flags are defined :
- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78

1
include/lib/cpus/aarch64/cortex_a76.h
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@ -20,6 +20,7 @@
#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
#define CORTEX_A76_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.

35
lib/cpus/aarch64/cortex_a76.S
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@ -419,6 +419,35 @@ func check_errata_1791580
b cpu_rev_var_ls
endfunc check_errata_1791580
/* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1800710.
* This applies to revision <= r4p0 of Cortex A76.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a76_1800710_wa
/* Compare x0 against revision <= r4p0 */
mov x17, x30
bl check_errata_1800710
cbz x0, 1f
/* Disable allocation of splintered pages in the L2 TLB */
mrs x1, CORTEX_A76_CPUECTLR_EL1
orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_53
msr CORTEX_A76_CPUECTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a76_1800710_wa
func check_errata_1800710
/* Applies to everything <= r4p0 */
mov x1, #0x40
b cpu_rev_var_ls
endfunc check_errata_1800710
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
@ -481,6 +510,11 @@ func cortex_a76_reset_func
bl errata_a76_1791580_wa
#endif
#if ERRATA_A76_1800710
mov x0, x18
bl errata_a76_1800710_wa
#endif
#if WORKAROUND_CVE_2018_3639
/* If the PE implements SSBS, we don't need the dynamic workaround */
mrs x0, id_aa64pfr1_el1
@ -562,6 +596,7 @@ func cortex_a76_errata_report
report_errata ERRATA_A76_1275112, cortex_a76, 1275112
report_errata ERRATA_A76_1286807, cortex_a76, 1286807
report_errata ERRATA_A76_1791580, cortex_a76, 1791580
report_errata ERRATA_A76_1800710, cortex_a76, 1800710
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184

8
lib/cpus/cpu-ops.mk
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@ -254,6 +254,10 @@ ERRATA_A76_1286807 ?=0
# only to revision <= r4p0 of the Cortex A76 cpu.
ERRATA_A76_1791580 ?=0
# Flag to apply erratum 1800710 workaround during reset. This erratum applies
# only to revision <= r4p0 of the Cortex A76 cpu.
ERRATA_A76_1800710 ?=0
# Flag to apply erratum 1688305 workaround during reset. This erratum applies
# to revisions r0p0 - r1p0 of the A78 cpu.
ERRATA_A78_1688305 ?=0
@ -495,6 +499,10 @@ $(eval $(call add_define,ERRATA_A76_1286807))
$(eval $(call assert_boolean,ERRATA_A76_1791580))
$(eval $(call add_define,ERRATA_A76_1791580))
# Process ERRATA_A76_1800710 flag
$(eval $(call assert_boolean,ERRATA_A76_1800710))
$(eval $(call add_define,ERRATA_A76_1800710))
# Process ERRATA_A78_1688305 flag
$(eval $(call assert_boolean,ERRATA_A78_1688305))
$(eval $(call add_define,ERRATA_A78_1688305))