Merge pull request #983 from dp-arm/dp/aarch32-errata
aarch32: Implement errata workarounds for Cortex A53 and A57
This commit is contained in:
commit
e036660aab
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@ -8,6 +8,7 @@
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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@ -176,6 +177,14 @@ void sp_min_main(void)
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* corresponding to the desired security state after the next ERET.
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*/
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sp_min_prepare_next_image_entry();
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/*
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* Perform any platform specific runtime setup prior to cold boot exit
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* from SP_MIN.
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*/
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sp_min_plat_runtime_setup();
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console_flush();
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}
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/******************************************************************************
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -12,8 +12,9 @@
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******************************************************************************/
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void sp_min_early_platform_setup(void *from_bl2,
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void *plat_params_from_bl2);
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void sp_min_plat_arch_setup(void);
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void sp_min_platform_setup(void);
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void sp_min_plat_runtime_setup(void);
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void sp_min_plat_arch_setup(void);
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entry_point_info_t *sp_min_plat_get_bl33_ep_info(void);
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#endif /* __PLATFORM_SP_MIN_H__ */
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@ -42,6 +42,8 @@
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******************************************************************************/
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#define CORTEX_A53_ACTLR p15, 0, c15
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#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT 44
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#define CORTEX_A53_ACTLR_ENDCCASCI (1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
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#define CORTEX_A53_ACTLR_DTAH (1 << 24)
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/*******************************************************************************
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@ -55,7 +55,7 @@
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 3
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#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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@ -37,7 +37,7 @@
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 3
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#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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@ -54,6 +54,9 @@
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#define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE
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#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
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#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
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#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
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@ -163,6 +163,7 @@ void arm_tsp_early_platform_setup(void);
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/* SP_MIN utility functions */
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void arm_sp_min_early_platform_setup(void *from_bl2,
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void *plat_params_from_bl2);
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void arm_sp_min_plat_runtime_setup(void);
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/* FIP TOC validity check */
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int arm_io_is_toc_valid(void);
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@ -10,6 +10,11 @@
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#include <cpu_macros.S>
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#include <debug.h>
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#if A53_DISABLE_NON_TEMPORAL_HINT
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#undef ERRATA_A53_836870
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#define ERRATA_A53_836870 1
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#endif
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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@ -23,11 +28,133 @@ func cortex_a53_disable_smp
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bx lr
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endfunc cortex_a53_disable_smp
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #826319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* --------------------------------------------------
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*/
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func errata_a53_826319_wa
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/*
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* Compare r0 against revision r0p2
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*/
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mov r2, lr
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bl check_errata_826319
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr r0, CORTEX_A53_L2ACTLR
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bic r0, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
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orr r0, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
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stcopr r0, CORTEX_A53_L2ACTLR
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1:
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bx lr
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endfunc errata_a53_826319_wa
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func check_errata_826319
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mov r1, #0x02
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b cpu_rev_var_ls
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endfunc check_errata_826319
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/* ---------------------------------------------------------------------
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* Disable the cache non-temporal hint.
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*
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* This ignores the Transient allocation hint in the MAIR and treats
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* allocations the same as non-transient allocation types. As a result,
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* the LDNP and STNP instructions in AArch64 behave the same as the
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* equivalent LDP and STP instructions.
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*
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* This is relevant only for revisions <= r0p3 of Cortex-A53.
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* From r0p4 and onwards, the bit to disable the hint is enabled by
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* default at reset.
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*
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------------------------
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*/
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func a53_disable_non_temporal_hint
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/*
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* Compare r0 against revision r0p3
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*/
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mov r2, lr
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bl check_errata_disable_non_temporal_hint
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A53_ACTLR
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orr64_imm r0, r1, CORTEX_A53_ACTLR_DTAH
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stcopr16 r0, r1, CORTEX_A53_ACTLR
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1:
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bx lr
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endfunc a53_disable_non_temporal_hint
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func check_errata_disable_non_temporal_hint
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mov r1, #0x03
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b cpu_rev_var_ls
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endfunc check_errata_disable_non_temporal_hint
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #855873.
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*
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* This applies only to revisions >= r0p3 of Cortex A53.
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* Earlier revisions of the core are affected as well, but don't
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* have the chicken bit in the CPUACTLR register. It is expected that
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* the rich OS takes care of that, especially as the workaround is
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* shared with other erratas in those revisions of the CPU.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* --------------------------------------------------
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*/
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func errata_a53_855873_wa
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/*
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* Compare r0 against revision r0p3 and higher
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*/
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mov r2, lr
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bl check_errata_855873
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A53_ACTLR
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orr64_imm r0, r1, CORTEX_A53_ACTLR_ENDCCASCI
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stcopr16 r0, r1, CORTEX_A53_ACTLR
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1:
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bx lr
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endfunc errata_a53_855873_wa
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func check_errata_855873
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mov r1, #0x03
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b cpu_rev_var_hs
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endfunc check_errata_855873
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A53.
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* Shall clobber: r0-r6
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* -------------------------------------------------
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*/
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func cortex_a53_reset_func
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mov r5, lr
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bl cpu_get_rev_var
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mov r4, r0
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#if ERRATA_A53_826319
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mov r0, r4
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bl errata_a53_826319_wa
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#endif
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#if ERRATA_A53_836870
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mov r0, r4
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bl a53_disable_non_temporal_hint
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#endif
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#if ERRATA_A53_855873
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mov r0, r4
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bl errata_a53_855873_wa
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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@ -36,7 +163,7 @@ func cortex_a53_reset_func
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orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
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stcopr16 r0, r1, CORTEX_A53_ECTLR
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isb
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bx lr
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bx r5
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endfunc cortex_a53_reset_func
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/* ----------------------------------------------------
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@ -111,6 +238,29 @@ func cortex_a53_cluster_pwr_dwn
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b cortex_a53_disable_smp
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endfunc cortex_a53_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A53. Must follow AAPCS.
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*/
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func cortex_a53_errata_report
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push {r12, lr}
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bl cpu_get_rev_var
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mov r4, r0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A53_826319, cortex_a53, 826319
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report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
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report_errata ERRATA_A53_855873, cortex_a53, 855873
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pop {r12, lr}
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bx lr
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endfunc cortex_a53_errata_report
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#endif
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
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cortex_a53_reset_func, \
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cortex_a53_core_pwr_dwn, \
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@ -50,11 +50,312 @@ func cortex_a57_disable_ext_debug
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bx lr
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endfunc cortex_a57_disable_ext_debug
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/* --------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #806969.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* --------------------------------------------------
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*/
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func errata_a57_806969_wa
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/*
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* Compare r0 against revision r0p0
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*/
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mov r2, lr
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bl check_errata_806969
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_ACTLR
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orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
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stcopr16 r0, r1, CORTEX_A57_ACTLR
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1:
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bx lr
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endfunc errata_a57_806969_wa
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func check_errata_806969
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mov r1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_806969
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #813419.
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* This applies only to revision r0p0 of Cortex A57.
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* ---------------------------------------------------
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*/
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func check_errata_813419
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/*
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* Even though this is only needed for revision r0p0, it
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* is always applied due to limitations of the current
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* errata framework.
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*/
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mov r0, #ERRATA_APPLIES
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bx lr
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endfunc check_errata_813419
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #813420.
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* This applies only to revision r0p0 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_813420_wa
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/*
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* Compare r0 against revision r0p0
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*/
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mov r2, lr
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bl check_errata_813420
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_ACTLR
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orr64_imm r0, r1, CORTEX_A57_ACTLR_DCC_AS_DCCI
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stcopr16 r0, r1, CORTEX_A57_ACTLR
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1:
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bx lr
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endfunc errata_a57_813420_wa
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func check_errata_813420
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mov r1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_813420
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/* --------------------------------------------------------------------
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* Disable the over-read from the LDNP instruction.
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*
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* This applies to all revisions <= r1p2. The performance degradation
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* observed with LDNP/STNP has been fixed on r1p3 and onwards.
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*
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------------------------
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*/
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func a57_disable_ldnp_overread
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/*
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* Compare r0 against revision r1p2
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*/
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mov r2, lr
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bl check_errata_disable_ldnp_overread
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_ACTLR
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orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_OVERREAD
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stcopr16 r0, r1, CORTEX_A57_ACTLR
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1:
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bx lr
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endfunc a57_disable_ldnp_overread
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func check_errata_disable_ldnp_overread
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mov r1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_disable_ldnp_overread
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #826974.
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* This applies only to revision <= r1p1 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ---------------------------------------------------
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*/
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func errata_a57_826974_wa
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/*
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* Compare r0 against revision r1p1
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*/
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mov r2, lr
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bl check_errata_826974
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_ACTLR
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orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
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stcopr16 r0, r1, CORTEX_A57_ACTLR
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1:
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bx lr
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endfunc errata_a57_826974_wa
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func check_errata_826974
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mov r1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_826974
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #826977.
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* This applies only to revision <= r1p1 of Cortex A57.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
|
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* ---------------------------------------------------
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*/
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func errata_a57_826977_wa
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/*
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* Compare r0 against revision r1p1
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*/
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mov r2, lr
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bl check_errata_826977
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mov lr, r2
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr16 r0, r1, CORTEX_A57_ACTLR
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orr64_imm r0, r1, CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
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stcopr16 r0, r1, CORTEX_A57_ACTLR
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1:
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bx lr
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endfunc errata_a57_826977_wa
|
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func check_errata_826977
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mov r1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_826977
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A57 Errata #828024.
|
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* This applies only to revision <= r1p1 of Cortex A57.
|
||||
* Inputs:
|
||||
* r0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: r0-r3
|
||||
* ---------------------------------------------------
|
||||
*/
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||||
func errata_a57_828024_wa
|
||||
/*
|
||||
* Compare r0 against revision r1p1
|
||||
*/
|
||||
mov r2, lr
|
||||
bl check_errata_828024
|
||||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
/*
|
||||
* Setting the relevant bits in CORTEX_A57_ACTLR has to be done in 2
|
||||
* instructions here because the resulting bitmask doesn't fit in a
|
||||
* 16-bit value so it cannot be encoded in a single instruction.
|
||||
*/
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_NO_ALLOC_WBWA
|
||||
orr64_imm r0, r1, (CORTEX_A57_ACTLR_DIS_L1_STREAMING | CORTEX_A57_ACTLR_DIS_STREAMING)
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_828024_wa
|
||||
|
||||
func check_errata_828024
|
||||
mov r1, #0x11
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_828024
|
||||
|
||||
/* ---------------------------------------------------
|
||||
* Errata Workaround for Cortex A57 Errata #829520.
|
||||
* This applies only to revision <= r1p2 of Cortex A57.
|
||||
* Inputs:
|
||||
* r0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: r0-r3
|
||||
* ---------------------------------------------------
|
||||
*/
|
||||
func errata_a57_829520_wa
|
||||
/*
|
||||
* Compare r0 against revision r1p2
|
||||
*/
|
||||
mov r2, lr
|
||||
bl check_errata_829520
|
||||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r0, r1, CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_829520_wa
|
||||
|
||||
func check_errata_829520
|
||||
mov r1, #0x12
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_829520
|
||||
|
||||
/* ---------------------------------------------------
|
||||
* Errata Workaround for Cortex A57 Errata #833471.
|
||||
* This applies only to revision <= r1p2 of Cortex A57.
|
||||
* Inputs:
|
||||
* r0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: r0-r3
|
||||
* ---------------------------------------------------
|
||||
*/
|
||||
func errata_a57_833471_wa
|
||||
/*
|
||||
* Compare r0 against revision r1p2
|
||||
*/
|
||||
mov r2, lr
|
||||
bl check_errata_833471
|
||||
mov lr, r2
|
||||
cmp r0, #ERRATA_NOT_APPLIES
|
||||
beq 1f
|
||||
ldcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
orr64_imm r1, r1, CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
|
||||
stcopr16 r0, r1, CORTEX_A57_ACTLR
|
||||
1:
|
||||
bx lr
|
||||
endfunc errata_a57_833471_wa
|
||||
|
||||
func check_errata_833471
|
||||
mov r1, #0x12
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_833471
|
||||
|
||||
/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Cortex-A57.
|
||||
* Shall clobber: r0-r6
|
||||
* -------------------------------------------------
|
||||
*/
|
||||
func cortex_a57_reset_func
|
||||
mov r5, lr
|
||||
bl cpu_get_rev_var
|
||||
mov r4, r0
|
||||
|
||||
#if ERRATA_A57_806969
|
||||
mov r0, r4
|
||||
bl errata_a57_806969_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A57_813420
|
||||
mov r0, r4
|
||||
bl errata_a57_813420_wa
|
||||
#endif
|
||||
|
||||
#if A57_DISABLE_NON_TEMPORAL_HINT
|
||||
mov r0, r4
|
||||
bl a57_disable_ldnp_overread
|
||||
#endif
|
||||
|
||||
#if ERRATA_A57_826974
|
||||
mov r0, r4
|
||||
bl errata_a57_826974_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A57_826977
|
||||
mov r0, r4
|
||||
bl errata_a57_826977_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A57_828024
|
||||
mov r0, r4
|
||||
bl errata_a57_828024_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A57_829520
|
||||
mov r0, r4
|
||||
bl errata_a57_829520_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A57_833471
|
||||
mov r0, r4
|
||||
bl errata_a57_833471_wa
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Enable the SMP bit.
|
||||
* ---------------------------------------------
|
||||
|
@ -63,7 +364,7 @@ func cortex_a57_reset_func
|
|||
orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
|
||||
stcopr16 r0, r1, CORTEX_A57_ECTLR
|
||||
isb
|
||||
bx lr
|
||||
bx r5
|
||||
endfunc cortex_a57_reset_func
|
||||
|
||||
/* ----------------------------------------------------
|
||||
|
@ -162,6 +463,36 @@ func cortex_a57_cluster_pwr_dwn
|
|||
b cortex_a57_disable_ext_debug
|
||||
endfunc cortex_a57_cluster_pwr_dwn
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Errata printing function for Cortex A57. Must follow AAPCS.
|
||||
*/
|
||||
func cortex_a57_errata_report
|
||||
push {r12, lr}
|
||||
|
||||
bl cpu_get_rev_var
|
||||
mov r4, r0
|
||||
|
||||
/*
|
||||
* Report all errata. The revision-variant information is passed to
|
||||
* checking functions of each errata.
|
||||
*/
|
||||
report_errata ERRATA_A57_806969, cortex_a57, 806969
|
||||
report_errata ERRATA_A57_813419, cortex_a57, 813419
|
||||
report_errata ERRATA_A57_813420, cortex_a57, 813420
|
||||
report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
|
||||
disable_ldnp_overread
|
||||
report_errata ERRATA_A57_826974, cortex_a57, 826974
|
||||
report_errata ERRATA_A57_826977, cortex_a57, 826977
|
||||
report_errata ERRATA_A57_828024, cortex_a57, 828024
|
||||
report_errata ERRATA_A57_829520, cortex_a57, 829520
|
||||
report_errata ERRATA_A57_833471, cortex_a57, 833471
|
||||
|
||||
pop {r12, lr}
|
||||
bx lr
|
||||
endfunc cortex_a57_errata_report
|
||||
#endif
|
||||
|
||||
declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
|
||||
cortex_a57_reset_func, \
|
||||
cortex_a57_core_pwr_dwn, \
|
||||
|
|
|
@ -182,6 +182,19 @@ func cpu_rev_var_ls
|
|||
bx lr
|
||||
endfunc cpu_rev_var_ls
|
||||
|
||||
/*
|
||||
* Compare the CPU's revision-variant (r0) with a given value (r1), for errata
|
||||
* application purposes. If the revision-variant is higher than or same as a
|
||||
* given value, indicates that errata applies; otherwise not.
|
||||
*/
|
||||
.globl cpu_rev_var_hs
|
||||
func cpu_rev_var_hs
|
||||
cmp r0, r1
|
||||
movge r0, #ERRATA_APPLIES
|
||||
movlt r0, #ERRATA_NOT_APPLIES
|
||||
bx lr
|
||||
endfunc cpu_rev_var_hs
|
||||
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* void print_errata_status(void);
|
||||
|
|
|
@ -56,6 +56,9 @@
|
|||
#define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
|
||||
#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
|
||||
|
||||
#define PLAT_ARM_SP_MIN_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
|
||||
#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
|
||||
|
||||
#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
|
||||
#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
|
||||
|
||||
|
|
|
@ -81,9 +81,9 @@ func JUNO_HANDLER(0)
|
|||
* Cortex-A57 specific settings
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
mov r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
|
||||
(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
|
||||
stcopr r0, L2CTLR
|
||||
mov r0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
|
||||
(CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT))
|
||||
stcopr r0, CORTEX_A57_L2CTLR
|
||||
1:
|
||||
isb
|
||||
bx lr
|
||||
|
@ -118,8 +118,8 @@ A57:
|
|||
* Cortex-A57 specific settings
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
mov r0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
|
||||
stcopr r0, L2CTLR
|
||||
mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
|
||||
stcopr r0, CORTEX_A57_L2CTLR
|
||||
isb
|
||||
bx lr
|
||||
endfunc JUNO_HANDLER(1)
|
||||
|
@ -152,9 +152,9 @@ A72:
|
|||
* Cortex-A72 specific settings
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
mov r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
|
||||
(L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
|
||||
stcopr r0, L2CTLR
|
||||
mov r0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
|
||||
(CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT))
|
||||
stcopr r0, CORTEX_A72_L2CTLR
|
||||
isb
|
||||
bx lr
|
||||
endfunc JUNO_HANDLER(2)
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
@ -127,6 +127,17 @@ void sp_min_early_platform_setup(void *from_bl2,
|
|||
plat_arm_interconnect_enter_coherency();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Perform any SP_MIN platform runtime setup prior to SP_MIN exit.
|
||||
* Common to ARM standard platforms.
|
||||
******************************************************************************/
|
||||
void arm_sp_min_plat_runtime_setup(void)
|
||||
{
|
||||
/* Initialize the runtime console */
|
||||
console_init(PLAT_ARM_SP_MIN_RUN_UART_BASE,
|
||||
PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ, ARM_CONSOLE_BAUDRATE);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Perform platform specific setup for SP_MIN
|
||||
******************************************************************************/
|
||||
|
@ -155,6 +166,11 @@ void sp_min_platform_setup(void)
|
|||
plat_arm_pwrc_setup();
|
||||
}
|
||||
|
||||
void sp_min_plat_runtime_setup(void)
|
||||
{
|
||||
arm_sp_min_plat_runtime_setup();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Perform the very early platform specific architectural setup here. At the
|
||||
* moment this only initializes the MMU
|
||||
|
|
|
@ -4,6 +4,7 @@
|
|||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <console.h>
|
||||
#include <platform.h>
|
||||
#include <xlat_mmu_helpers.h>
|
||||
|
||||
|
@ -13,8 +14,18 @@
|
|||
* platforms but may also be overridden by a platform if required.
|
||||
*/
|
||||
#pragma weak bl32_plat_enable_mmu
|
||||
#pragma weak sp_min_plat_runtime_setup
|
||||
|
||||
void bl32_plat_enable_mmu(uint32_t flags)
|
||||
{
|
||||
enable_mmu_secure(flags);
|
||||
}
|
||||
|
||||
void sp_min_plat_runtime_setup(void)
|
||||
{
|
||||
/*
|
||||
* Finish the use of console driver in SP_MIN so that any runtime logs
|
||||
* from SP_MIN will be suppressed.
|
||||
*/
|
||||
console_uninit();
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue