feat(plat/nxp/ls1043ardb): add ls1043ardb board support
The LS1043A reference design board (RDB) is a computing, evaluation, and development platform that supports the Layerscape LS1043A architecture processor. The old implementation in tf-a (plat/layerscape/board/ls1043/) is removed, and this patch is adding it back, it is using the unified software component and architecture with all the other Layerscape platforms. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Change-Id: I83eee2f9254267b148960b05e25b6c9ba86cf07e
This commit is contained in:
Jiafei Pan
parent
3b0de91825
commit
e4bd65fed8
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <ddr.h>
|
||||
#include <lib/utils.h>
|
||||
|
||||
#include <errata.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
#ifdef CONFIG_STATIC_DDR
|
||||
const struct ddr_cfg_regs static_1600 = {
|
||||
.cs[0].config = U(0x80040322),
|
||||
.cs[0].bnds = U(0x7F),
|
||||
.sdram_cfg[0] = U(0xC50C0000),
|
||||
.sdram_cfg[1] = U(0x401100),
|
||||
.timing_cfg[0] = U(0x91550018),
|
||||
.timing_cfg[1] = U(0xBBB48C42),
|
||||
.timing_cfg[2] = U(0x48C111),
|
||||
.timing_cfg[3] = U(0x10C1000),
|
||||
.timing_cfg[4] = U(0x2),
|
||||
.timing_cfg[5] = U(0x3401400),
|
||||
.timing_cfg[7] = U(0x13300000),
|
||||
.timing_cfg[8] = U(0x2115600),
|
||||
.sdram_mode[0] = U(0x3010210),
|
||||
.sdram_mode[9] = U(0x4000000),
|
||||
.sdram_mode[8] = U(0x500),
|
||||
.sdram_mode[2] = U(0x10210),
|
||||
.sdram_mode[10] = U(0x400),
|
||||
.sdram_mode[11] = U(0x4000000),
|
||||
.sdram_mode[4] = U(0x10210),
|
||||
.sdram_mode[12] = U(0x400),
|
||||
.sdram_mode[13] = U(0x4000000),
|
||||
.sdram_mode[6] = U(0x10210),
|
||||
.sdram_mode[14] = U(0x400),
|
||||
.sdram_mode[15] = U(0x4000000),
|
||||
.interval = U(0x18600618),
|
||||
.zq_cntl = U(0x8A090705),
|
||||
.clk_cntl = U(0x3000000),
|
||||
.cdr[0] = U(0x80040000),
|
||||
.cdr[1] = U(0xA181),
|
||||
.wrlvl_cntl[0] = U(0x8675F607),
|
||||
.wrlvl_cntl[1] = U(0x7090807,
|
||||
.wrlvl_cntl[2] = U(0x7070707),
|
||||
.debug[28] = U(0x00700046),
|
||||
};
|
||||
|
||||
uint64_t board_static_ddr(struct ddr_info *priv)
|
||||
{
|
||||
memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
|
||||
|
||||
return ULL(0x80000000);
|
||||
}
|
||||
|
||||
#else
|
||||
static const struct rc_timing rcz[] = {
|
||||
{1600, 12, 7},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_timing ram[] = {
|
||||
{0x1f, rcz, 0x00020100, 0},
|
||||
};
|
||||
|
||||
int ddr_board_options(struct ddr_info *priv)
|
||||
{
|
||||
int ret;
|
||||
struct memctl_opt *popts = &priv->opt;
|
||||
|
||||
ret = cal_board_params(priv, ram, ARRAY_SIZE(ram));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
popts->cpo_sample = U(0x46);
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
|
||||
DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
|
||||
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* DDR model number: MT40A512M8HX-093E */
|
||||
struct dimm_params ddr_raw_timing = {
|
||||
.n_ranks = U(1),
|
||||
.rank_density = ULL(2147483648),
|
||||
.capacity = ULL(2147483648),
|
||||
.primary_sdram_width = U(32),
|
||||
.n_row_addr = U(15),
|
||||
.n_col_addr = U(10),
|
||||
.bank_group_bits = U(2),
|
||||
.burst_lengths_bitmask = U(0x0c),
|
||||
.tckmin_x_ps = 938,
|
||||
.tckmax_ps = 1500,
|
||||
.caslat_x = U(0x000DFA00),
|
||||
.taa_ps = 13500,
|
||||
.trcd_ps = 13500,
|
||||
.trp_ps = 13500,
|
||||
.tras_ps = 33000,
|
||||
.trc_ps = 46500,
|
||||
.twr_ps = 15000,
|
||||
.trfc1_ps = 260000,
|
||||
.trfc2_ps = 160000,
|
||||
.trfc4_ps = 110000,
|
||||
.tfaw_ps = 21000,
|
||||
.trrds_ps = 3700,
|
||||
.trrdl_ps = 5300,
|
||||
.tccdl_ps = 5355,
|
||||
.refresh_rate_ps = U(7800000),
|
||||
.rc = U(0x1f),
|
||||
};
|
||||
|
||||
int ddr_get_ddr_params(struct dimm_params *pdimm,
|
||||
struct ddr_conf *conf)
|
||||
{
|
||||
static const char dimm_model[] = "Fixed DDR on board";
|
||||
|
||||
conf->dimm_in_use[0] = 1;
|
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
|
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
int64_t init_ddr(void)
|
||||
{
|
||||
struct ddr_info info;
|
||||
struct sysinfo sys;
|
||||
int64_t dram_size;
|
||||
|
||||
zeromem(&sys, sizeof(sys));
|
||||
get_clocks(&sys);
|
||||
debug("platform clock %lu\n", sys.freq_platform);
|
||||
debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
|
||||
debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
|
||||
|
||||
zeromem(&info, sizeof(struct ddr_info));
|
||||
info.num_ctlrs = 1;
|
||||
info.dimm_on_ctlr = 1;
|
||||
info.clk = get_ddr_freq(&sys, 0);
|
||||
info.ddr[0] = (void *)NXP_DDR_ADDR;
|
||||
|
||||
dram_size = dram_init(&info);
|
||||
|
||||
if (dram_size < 0) {
|
||||
ERROR("DDR init failed\n");
|
||||
}
|
||||
|
||||
#ifdef ERRATA_SOC_A008850
|
||||
erratum_a008850_post();
|
||||
#endif
|
||||
return dram_size;
|
||||
}
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_DEF_H
|
||||
#define PLAT_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
/*
|
||||
* Required without TBBR.
|
||||
* To include the defines for DDR PHY Images.
|
||||
*/
|
||||
#include <tbbr_img_def.h>
|
||||
|
||||
#include "policy.h"
|
||||
#include <soc.h>
|
||||
|
||||
#define NXP_SPD_EEPROM0 0x51
|
||||
|
||||
#define NXP_SYSCLK_FREQ 100000000
|
||||
#define NXP_DDRCLK_FREQ 100000000
|
||||
|
||||
/* UART related definition */
|
||||
#define NXP_CONSOLE_ADDR NXP_UART_ADDR
|
||||
#define NXP_CONSOLE_BAUDRATE 115200
|
||||
|
||||
/* Size of cacheable stacks */
|
||||
#if defined(IMAGE_BL2)
|
||||
#if defined(TRUSTED_BOARD_BOOT)
|
||||
#define PLATFORM_STACK_SIZE 0x2000
|
||||
#else
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
#elif defined(IMAGE_BL31)
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
/* SD block buffer */
|
||||
#define NXP_SD_BLOCK_BUF_SIZE (0x00100000)
|
||||
#define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000)
|
||||
|
||||
#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
|
||||
|
||||
/* IO defines as needed by IO driver framework */
|
||||
#define MAX_IO_DEVICES 3
|
||||
#define MAX_IO_BLOCK_DEVICES 1
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
/*
|
||||
* FIP image defines - Offset at which FIP Image would be present
|
||||
* Image would include Bl31 , Bl33 and Bl32 (optional)
|
||||
*/
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
#define MAX_FIP_DEVICES 2
|
||||
#endif
|
||||
|
||||
#ifndef MAX_FIP_DEVICES
|
||||
#define MAX_FIP_DEVICES 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ID of the secure physical generic timer interrupt used by the BL32.
|
||||
*/
|
||||
#define BL32_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
/*
|
||||
* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define PLAT_LS_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
#define PLAT_LS_G0_IRQ_PROPS(grp)
|
||||
|
||||
#endif /* PLAT_DEF_H */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <plat_common.h>
|
||||
|
||||
#pragma weak board_enable_povdd
|
||||
#pragma weak board_disable_povdd
|
||||
|
||||
bool board_enable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
bool board_disable_povdd(void)
|
||||
{
|
||||
#ifdef CONFIG_POVDD_ENABLE
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
#
|
||||
# Copyright 2018-2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# board-specific build parameters
|
||||
|
||||
BOOT_MODE ?= nor
|
||||
BOARD := ls1043ardb
|
||||
POVDD_ENABLE := no
|
||||
|
||||
# DDR Compilation Configs
|
||||
CONFIG_DDR_NODIMM := 1
|
||||
NUM_OF_DDRC := 1
|
||||
DDRC_NUM_DIMM := 0
|
||||
DDRC_NUM_CS := 4
|
||||
DDR_ECC_EN := no
|
||||
CONFIG_STATIC_DDR := 0
|
||||
|
||||
# On-Board Flash Details
|
||||
# 128MB IFC NOR Flash
|
||||
NOR_FLASH_SZ := 0x8000000
|
||||
|
||||
# Platform specific features.
|
||||
WARM_BOOT := no
|
||||
|
||||
# Adding Platform files build files
|
||||
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
|
||||
${BOARD_PATH}/platform.c
|
||||
|
||||
SUPPORTED_BOOT_MODE := nor \
|
||||
sd \
|
||||
nand
|
||||
|
||||
# Adding platform board build info
|
||||
include plat/nxp/common/plat_make_helper/plat_common_def.mk
|
||||
|
||||
# Adding SoC build info
|
||||
include plat/nxp/soc-ls1043a/soc.mk
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <plat_def.h>
|
||||
#include <plat_default_def.h>
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef POLICY_H
|
||||
#define POLICY_H
|
||||
|
||||
/*
|
||||
* Set this to 0x0 to leave the default SMMU page size in sACR
|
||||
* Set this to 0x1 to change the SMMU page size to 64K
|
||||
*/
|
||||
#define POLICY_SMMU_PAGESZ_64K 0x1
|
||||
|
||||
#endif /* POLICY_H */
|
||||
Loading…
Reference in New Issue