Tegra194: platform handler for entering CPU standby state
This patch implements a handler to enter the standby state on Tegra194 platforms. On receiving a CPU_STANDBY state request, the platform handler issues TEGRA_NVG_CORE_C6 request to the MCE firmware to take the CPU into the standby state. Change-Id: I703a96ec12205853ddb3c3871b23e338e1f60687 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -77,6 +77,12 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
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/* Sanity check the requested state id */
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/* Sanity check the requested state id */
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switch (state_id) {
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switch (state_id) {
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case PSTATE_ID_CORE_IDLE:
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case PSTATE_ID_CORE_IDLE:
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/* Core idle request */
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
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req_state->pwr_domain_state[MPIDR_AFFLVL1] = PSCI_LOCAL_STATE_RUN;
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break;
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case PSTATE_ID_CORE_POWERDN:
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case PSTATE_ID_CORE_POWERDN:
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/* Core powerdown request */
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/* Core powerdown request */
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@ -94,6 +100,25 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
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return ret;
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return ret;
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}
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}
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int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
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{
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uint32_t cpu = plat_my_core_pos();
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mce_cstate_info_t cstate_info = { 0 };
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/* Program default wake mask */
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cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK;
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cstate_info.update_wake_mask = 1;
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mce_update_cstate_info(&cstate_info);
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/* Enter CPU idle */
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(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
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(uint64_t)TEGRA_NVG_CORE_C6,
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t19x_percpu_data[cpu].wake_time,
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0U);
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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{
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const plat_local_state_t *pwr_domain_state;
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const plat_local_state_t *pwr_domain_state;
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@ -118,15 +143,13 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
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stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
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TEGRA194_STATE_ID_MASK;
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TEGRA194_STATE_ID_MASK;
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if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
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if ((stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
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(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
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/* Enter CPU idle/powerdown */
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/* Enter CPU powerdown */
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val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
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(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
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(uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
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(uint64_t)TEGRA_NVG_CORE_C7,
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ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
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t19x_percpu_data[cpu].wake_time,
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t19x_percpu_data[cpu].wake_time, 0);
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0U);
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assert(ret == 0);
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} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
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