Merge pull request #727 from soby-mathew/sm/PSCI_lib_doc
AArch32: Update user-guide and add DTBs
This commit is contained in:
danh-arm
GitHub
commit
ea68f8c774
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@ -89,23 +89,50 @@ Download the Trusted Firmware source code from Github:
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---------------------------------
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---------------------------------
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* Before building Trusted Firmware, the environment variable `CROSS_COMPILE`
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* Before building Trusted Firmware, the environment variable `CROSS_COMPILE`
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must point to the Linaro cross compiler:
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must point to the Linaro cross compiler.
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For AArch64:
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export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
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export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
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* Change to the root directory of the Trusted Firmware source tree and build:
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For AArch32:
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export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
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* Change to the root directory of the Trusted Firmware source tree and build.
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For AArch64:
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make PLAT=<platform> all
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make PLAT=<platform> all
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Notes:
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For AArch32:
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make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
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Notes:
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* If `PLAT` is not specified, `fvp` is assumed by default. See the
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* If `PLAT` is not specified, `fvp` is assumed by default. See the
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"Summary of build options" for more information on available build
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"Summary of build options" for more information on available build
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options.
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options.
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* The TSP (Test Secure Payload), corresponding to the BL32 image, is not
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* (AArch32 only) Currently only `PLAT=fvp` is supported. Please note that
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compiled in by default. Refer to the "Building the Test Secure Payload"
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AArch32 support for Normal world boot loader (BL33), like U-boot or
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section below.
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UEFI, on FVP is not available upstream. Hence custom solutions are
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required to allow Linux boot on FVP. The build instructions below
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assume such a custom boot loader (BL33) is available.
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* (AArch32 only) `AARCH32_SP` is the AArch32 EL3 Runtime Software and it
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corresponds to the BL32 image. A minimal `AARCH32_SP`, sp_min, is
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provided by ARM Trusted Firmware to demonstrate how PSCI Library can
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be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3
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Runtime Software may include other runtime services, for example
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Trusted OS services. A guide to integrate PSCI library with AArch32
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EL3 Runtime Software can be found [here][PSCI Lib Integration].
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* (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
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image, is not compiled in by default. Refer to the "Building the Test
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Secure Payload" section below.
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* By default this produces a release version of the build. To produce a
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* By default this produces a release version of the build. To produce a
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debug version instead, refer to the "Debugging options" section below.
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debug version instead, refer to the "Debugging options" section below.
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@ -117,7 +144,8 @@ Download the Trusted Firmware source code from Github:
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* `build/<platform>/<build-type>/bl1.bin`
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* `build/<platform>/<build-type>/bl1.bin`
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* `build/<platform>/<build-type>/bl2.bin`
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* `build/<platform>/<build-type>/bl2.bin`
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* `build/<platform>/<build-type>/bl31.bin`
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* `build/<platform>/<build-type>/bl31.bin` (AArch64 only)
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* `build/<platform>/<build-type>/bl32.bin` (mandatory for AArch32)
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where `<platform>` is the name of the chosen platform and `<build-type>`
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where `<platform>` is the name of the chosen platform and `<build-type>`
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is either `debug` or `release`. The actual number of images might differ
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is either `debug` or `release`. The actual number of images might differ
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@ -238,6 +266,12 @@ performed.
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entrypoint) or 1 (CPU reset to BL31 entrypoint).
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entrypoint) or 1 (CPU reset to BL31 entrypoint).
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The default value is 0.
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The default value is 0.
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* `RESET_TO_SP_MIN`: SP_MIN is the minimal AArch32 Secure Payload provided in
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ARM Trusted Firmware. This flag configures SP_MIN entrypoint as the CPU
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reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU
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reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default
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value is 0.
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* `CRASH_REPORTING`: A non-zero value enables a console dump of processor
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* `CRASH_REPORTING`: A non-zero value enables a console dump of processor
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register state when an unexpected exception occurs during execution of
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register state when an unexpected exception occurs during execution of
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BL31. This option defaults to the value of `DEBUG` - i.e. by default
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BL31. This option defaults to the value of `DEBUG` - i.e. by default
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@ -600,7 +634,6 @@ An additional boot loader binary file is created in the `build` directory:
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`build/<platform>/<build-type>/bl32.bin`
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`build/<platform>/<build-type>/bl32.bin`
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### Checking source code style
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### Checking source code style
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When making changes to the source for submission to the project, the source
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When making changes to the source for submission to the project, the source
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@ -1042,8 +1075,8 @@ JTAG on Juno.
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9. Running the software on FVP
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9. Running the software on FVP
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-------------------------------
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-------------------------------
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This version of the ARM Trusted Firmware has been tested on the following ARM
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The AArch64 build of this version of ARM Trusted Firmware has been tested on
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FVPs (64-bit versions only).
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the following ARM FVPs (64-bit host machine only).
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* `Foundation_Platform` (Version 10.1, Build 10.1.32)
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* `Foundation_Platform` (Version 10.1, Build 10.1.32)
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* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701)
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* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701)
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@ -1051,6 +1084,12 @@ FVPs (64-bit versions only).
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* `FVP_Base_Cortex-A57x1-A53x1` (Version 7.7, Build 0.8.7701)
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* `FVP_Base_Cortex-A57x1-A53x1` (Version 7.7, Build 0.8.7701)
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* `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701)
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* `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701)
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The AArch32 build of this version of ARM Trusted Firmware has been tested on
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the following ARM FVPs (64-bit host machine only).
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* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701)
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* `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32)
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NOTE: The build numbers quoted above are those reported by launching the FVP
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NOTE: The build numbers quoted above are those reported by launching the FVP
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with the `--version` parameter.
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with the `--version` parameter.
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@ -1082,11 +1121,21 @@ all FDTs are available from there.
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For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
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For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
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Base memory map configuration.
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Base memory map configuration.
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* `fvp-base-gicv2-psci-aarch32.dtb`
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For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
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with Base memory map configuration.
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* `fvp-base-gicv3-psci.dtb`
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* `fvp-base-gicv3-psci.dtb`
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(Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
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(Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base
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memory map configuration and Linux GICv3 support.
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memory map configuration and Linux GICv3 support.
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* `fvp-base-gicv3-psci-aarch32.dtb`
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For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state
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with Base memory map configuration and Linux GICv3 support.
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* `fvp-foundation-gicv2-psci.dtb`
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* `fvp-foundation-gicv2-psci.dtb`
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For use with Foundation FVP with Base memory map configuration.
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For use with Foundation FVP with Base memory map configuration.
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@ -1099,7 +1148,7 @@ all FDTs are available from there.
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### Running on the Foundation FVP with reset to BL1 entrypoint
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### Running on the Foundation FVP with reset to BL1 entrypoint
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The following `Foundation_Platform` parameters should be used to boot Linux with
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The following `Foundation_Platform` parameters should be used to boot Linux with
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4 CPUs using the ARM Trusted Firmware.
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4 CPUs using the AArch64 build of ARM Trusted Firmware.
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<path-to>/Foundation_Platform \
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<path-to>/Foundation_Platform \
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--cores=4 \
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--cores=4 \
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@ -1124,7 +1173,7 @@ Notes:
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### Running on the AEMv8 Base FVP with reset to BL1 entrypoint
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### Running on the AEMv8 Base FVP with reset to BL1 entrypoint
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The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
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The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
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with 8 CPUs using the ARM Trusted Firmware.
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with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C pctl.startup=0.0.0.0 \
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@ -1139,10 +1188,36 @@ with 8 CPUs using the ARM Trusted Firmware.
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
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### Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
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The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
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with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.CONFIG64=0 \
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-C cluster0.cpu1.CONFIG64=0 \
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-C cluster0.cpu2.CONFIG64=0 \
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-C cluster0.cpu3.CONFIG64=0 \
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-C cluster1.cpu0.CONFIG64=0 \
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-C cluster1.cpu1.CONFIG64=0 \
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-C cluster1.cpu2.CONFIG64=0 \
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-C cluster1.cpu3.CONFIG64=0 \
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-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
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-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x83000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
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### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
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### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
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The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
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The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
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boot Linux with 8 CPUs using the ARM Trusted Firmware.
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boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
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<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
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<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
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-C pctl.startup=0.0.0.0 \
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-C pctl.startup=0.0.0.0 \
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@ -1155,10 +1230,26 @@ boot Linux with 8 CPUs using the ARM Trusted Firmware.
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
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### Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
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The following `FVP_Base_Cortex-A32x4` model parameters should be used to
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boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
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<path-to>/FVP_Base_Cortex-A32x4 \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cache_state_modelled=1 \
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-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
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-C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x83000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
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### Running on the AEMv8 Base FVP with reset to BL31 entrypoint
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### Running on the AEMv8 Base FVP with reset to BL31 entrypoint
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The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
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The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
|
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with 8 CPUs using the ARM Trusted Firmware.
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with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C pctl.startup=0.0.0.0 \
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@ -1199,10 +1290,47 @@ Notes:
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`--data="<path-to><bl32-binary>"@<base-address-of-bl32>` to the new value of
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`--data="<path-to><bl32-binary>"@<base-address-of-bl32>` to the new value of
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`BL32_BASE`.
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`BL32_BASE`.
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### Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
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The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
|
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with 8 CPUs using the AArch32 build of ARM Trusted Firmware.
|
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|
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.CONFIG64=0 \
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-C cluster0.cpu1.CONFIG64=0 \
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-C cluster0.cpu2.CONFIG64=0 \
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-C cluster0.cpu3.CONFIG64=0 \
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-C cluster1.cpu0.CONFIG64=0 \
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||||||
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-C cluster1.cpu1.CONFIG64=0 \
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||||||
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-C cluster1.cpu2.CONFIG64=0 \
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-C cluster1.cpu3.CONFIG64=0 \
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-C cluster0.cpu0.RVBAR=0x04001000 \
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-C cluster0.cpu1.RVBAR=0x04001000 \
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-C cluster0.cpu2.RVBAR=0x04001000 \
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-C cluster0.cpu3.RVBAR=0x04001000 \
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-C cluster1.cpu0.RVBAR=0x04001000 \
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-C cluster1.cpu1.RVBAR=0x04001000 \
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-C cluster1.cpu2.RVBAR=0x04001000 \
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-C cluster1.cpu3.RVBAR=0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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||||||
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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||||||
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--data cluster0.cpu0="<path-to>/<fdt>"@0x83000000 \
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||||||
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||||
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-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
|
||||||
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|
||||||
|
Note: The load address of `<bl32-binary>` depends on the value `BL32_BASE`.
|
||||||
|
It should match the address programmed into the RVBAR register as well.
|
||||||
|
|
||||||
### Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
|
### Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
|
||||||
|
|
||||||
The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
|
The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
|
||||||
boot Linux with 8 CPUs using the ARM Trusted Firmware.
|
boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
|
||||||
|
|
||||||
<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
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<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
|
||||||
-C pctl.startup=0.0.0.0 \
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-C pctl.startup=0.0.0.0 \
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||||||
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|
@ -1224,6 +1352,25 @@ boot Linux with 8 CPUs using the ARM Trusted Firmware.
|
||||||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||||
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
|
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
|
||||||
|
|
||||||
|
### Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
|
||||||
|
|
||||||
|
The following `FVP_Base_Cortex-A32x4` model parameters should be used to
|
||||||
|
boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware.
|
||||||
|
|
||||||
|
<path-to>/FVP_Base_Cortex-A32x4 \
|
||||||
|
-C pctl.startup=0.0.0.0 \
|
||||||
|
-C bp.secure_memory=1 \
|
||||||
|
-C bp.tzc_400.diagnostics=1 \
|
||||||
|
-C cache_state_modelled=1 \
|
||||||
|
-C cluster0.cpu0.RVBARADDR=0x04001000 \
|
||||||
|
-C cluster0.cpu1.RVBARADDR=0x04001000 \
|
||||||
|
-C cluster0.cpu2.RVBARADDR=0x04001000 \
|
||||||
|
-C cluster0.cpu3.RVBARADDR=0x04001000 \
|
||||||
|
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
|
||||||
|
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
|
||||||
|
--data cluster0.cpu0="<path-to>/<fdt>"@0x83000000 \
|
||||||
|
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||||
|
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
|
||||||
|
|
||||||
10. Running the software on Juno
|
10. Running the software on Juno
|
||||||
---------------------------------
|
---------------------------------
|
||||||
|
|
@ -1280,3 +1427,4 @@ _Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._
|
||||||
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)"
|
[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)"
|
||||||
[Trusted Board Boot]: trusted-board-boot.md
|
[Trusted Board Boot]: trusted-board-boot.md
|
||||||
[Firmware Update]: ./firmware-update.md
|
[Firmware Update]: ./firmware-update.md
|
||||||
|
[PSCI Lib Integration]: ./psci-lib-integration-guide.md
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -0,0 +1,331 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
* list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
* to endorse or promote products derived from this software without specific
|
||||||
|
* prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/memreserve/ 0x80000000 0x00010000;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
};
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "FVP Base";
|
||||||
|
compatible = "arm,vfp-base", "arm,vexpress";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
chosen { };
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &v2m_serial0;
|
||||||
|
serial1 = &v2m_serial1;
|
||||||
|
serial2 = &v2m_serial2;
|
||||||
|
serial3 = &v2m_serial3;
|
||||||
|
};
|
||||||
|
|
||||||
|
psci {
|
||||||
|
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
|
||||||
|
method = "smc";
|
||||||
|
cpu_suspend = <0x84000001>;
|
||||||
|
cpu_off = <0x84000002>;
|
||||||
|
cpu_on = <0x84000003>;
|
||||||
|
sys_poweroff = <0x84000008>;
|
||||||
|
sys_reset = <0x84000009>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu-map {
|
||||||
|
cluster0 {
|
||||||
|
core0 {
|
||||||
|
cpu = <&CPU0>;
|
||||||
|
};
|
||||||
|
core1 {
|
||||||
|
cpu = <&CPU1>;
|
||||||
|
};
|
||||||
|
core2 {
|
||||||
|
cpu = <&CPU2>;
|
||||||
|
};
|
||||||
|
core3 {
|
||||||
|
cpu = <&CPU3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cluster1 {
|
||||||
|
core0 {
|
||||||
|
cpu = <&CPU4>;
|
||||||
|
};
|
||||||
|
core1 {
|
||||||
|
cpu = <&CPU5>;
|
||||||
|
};
|
||||||
|
core2 {
|
||||||
|
cpu = <&CPU6>;
|
||||||
|
};
|
||||||
|
core3 {
|
||||||
|
cpu = <&CPU7>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
idle-states {
|
||||||
|
entry-method = "arm,psci";
|
||||||
|
|
||||||
|
CPU_SLEEP_0: cpu-sleep-0 {
|
||||||
|
compatible = "arm,idle-state";
|
||||||
|
local-timer-stop;
|
||||||
|
arm,psci-suspend-param = <0x0010000>;
|
||||||
|
entry-latency-us = <40>;
|
||||||
|
exit-latency-us = <100>;
|
||||||
|
min-residency-us = <150>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||||
|
compatible = "arm,idle-state";
|
||||||
|
local-timer-stop;
|
||||||
|
arm,psci-suspend-param = <0x1010000>;
|
||||||
|
entry-latency-us = <500>;
|
||||||
|
exit-latency-us = <1000>;
|
||||||
|
min-residency-us = <2500>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU0:cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x0>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU1:cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x1>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU2:cpu@2 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x2>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU3:cpu@3 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x3>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU4:cpu@100 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x100>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU5:cpu@101 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x101>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU6:cpu@102 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x102>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU7:cpu@103 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x103>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
L2_0: l2-cache0 {
|
||||||
|
compatible = "cache";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@80000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x80000000 0 0x7F000000>,
|
||||||
|
<0x00000008 0x80000000 0 0x80000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gic: interrupt-controller@2f000000 {
|
||||||
|
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
#address-cells = <0>;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0x0 0x2f000000 0 0x10000>,
|
||||||
|
<0x0 0x2c000000 0 0x2000>,
|
||||||
|
<0x0 0x2c010000 0 0x2000>,
|
||||||
|
<0x0 0x2c02F000 0 0x2000>;
|
||||||
|
interrupts = <1 9 0xf04>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupts = <1 13 0xff01>,
|
||||||
|
<1 14 0xff01>,
|
||||||
|
<1 11 0xff01>,
|
||||||
|
<1 10 0xff01>;
|
||||||
|
clock-frequency = <100000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@2a810000 {
|
||||||
|
compatible = "arm,armv7-timer-mem";
|
||||||
|
reg = <0x0 0x2a810000 0x0 0x10000>;
|
||||||
|
clock-frequency = <100000000>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
frame@2a830000 {
|
||||||
|
frame-number = <1>;
|
||||||
|
interrupts = <0 26 4>;
|
||||||
|
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pmu {
|
||||||
|
compatible = "arm,armv8-pmuv3";
|
||||||
|
interrupts = <0 60 4>,
|
||||||
|
<0 61 4>,
|
||||||
|
<0 62 4>,
|
||||||
|
<0 63 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
smb {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||||
|
<1 0 0 0x14000000 0x04000000>,
|
||||||
|
<2 0 0 0x18000000 0x04000000>,
|
||||||
|
<3 0 0 0x1c000000 0x04000000>,
|
||||||
|
<4 0 0 0x0c000000 0x04000000>,
|
||||||
|
<5 0 0 0x10000000 0x04000000>;
|
||||||
|
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-map-mask = <0 0 63>;
|
||||||
|
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||||
|
<0 0 1 &gic 0 1 4>,
|
||||||
|
<0 0 2 &gic 0 2 4>,
|
||||||
|
<0 0 3 &gic 0 3 4>,
|
||||||
|
<0 0 4 &gic 0 4 4>,
|
||||||
|
<0 0 5 &gic 0 5 4>,
|
||||||
|
<0 0 6 &gic 0 6 4>,
|
||||||
|
<0 0 7 &gic 0 7 4>,
|
||||||
|
<0 0 8 &gic 0 8 4>,
|
||||||
|
<0 0 9 &gic 0 9 4>,
|
||||||
|
<0 0 10 &gic 0 10 4>,
|
||||||
|
<0 0 11 &gic 0 11 4>,
|
||||||
|
<0 0 12 &gic 0 12 4>,
|
||||||
|
<0 0 13 &gic 0 13 4>,
|
||||||
|
<0 0 14 &gic 0 14 4>,
|
||||||
|
<0 0 15 &gic 0 15 4>,
|
||||||
|
<0 0 16 &gic 0 16 4>,
|
||||||
|
<0 0 17 &gic 0 17 4>,
|
||||||
|
<0 0 18 &gic 0 18 4>,
|
||||||
|
<0 0 19 &gic 0 19 4>,
|
||||||
|
<0 0 20 &gic 0 20 4>,
|
||||||
|
<0 0 21 &gic 0 21 4>,
|
||||||
|
<0 0 22 &gic 0 22 4>,
|
||||||
|
<0 0 23 &gic 0 23 4>,
|
||||||
|
<0 0 24 &gic 0 24 4>,
|
||||||
|
<0 0 25 &gic 0 25 4>,
|
||||||
|
<0 0 26 &gic 0 26 4>,
|
||||||
|
<0 0 27 &gic 0 27 4>,
|
||||||
|
<0 0 28 &gic 0 28 4>,
|
||||||
|
<0 0 29 &gic 0 29 4>,
|
||||||
|
<0 0 30 &gic 0 30 4>,
|
||||||
|
<0 0 31 &gic 0 31 4>,
|
||||||
|
<0 0 32 &gic 0 32 4>,
|
||||||
|
<0 0 33 &gic 0 33 4>,
|
||||||
|
<0 0 34 &gic 0 34 4>,
|
||||||
|
<0 0 35 &gic 0 35 4>,
|
||||||
|
<0 0 36 &gic 0 36 4>,
|
||||||
|
<0 0 37 &gic 0 37 4>,
|
||||||
|
<0 0 38 &gic 0 38 4>,
|
||||||
|
<0 0 39 &gic 0 39 4>,
|
||||||
|
<0 0 40 &gic 0 40 4>,
|
||||||
|
<0 0 41 &gic 0 41 4>,
|
||||||
|
<0 0 42 &gic 0 42 4>;
|
||||||
|
|
||||||
|
/include/ "rtsm_ve-motherboard.dtsi"
|
||||||
|
};
|
||||||
|
|
||||||
|
panels {
|
||||||
|
panel@0 {
|
||||||
|
compatible = "panel";
|
||||||
|
mode = "XVGA";
|
||||||
|
refresh = <60>;
|
||||||
|
xres = <1024>;
|
||||||
|
yres = <768>;
|
||||||
|
pixclock = <15748>;
|
||||||
|
left_margin = <152>;
|
||||||
|
right_margin = <48>;
|
||||||
|
upper_margin = <23>;
|
||||||
|
lower_margin = <3>;
|
||||||
|
hsync_len = <104>;
|
||||||
|
vsync_len = <4>;
|
||||||
|
sync = <0>;
|
||||||
|
vmode = "FB_VMODE_NONINTERLACED";
|
||||||
|
tim2 = "TIM2_BCD", "TIM2_IPC";
|
||||||
|
cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
|
||||||
|
caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
|
||||||
|
bpp = <16>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
Binary file not shown.
|
|
@ -0,0 +1,340 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
* list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
* to endorse or promote products derived from this software without specific
|
||||||
|
* prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/memreserve/ 0x80000000 0x00010000;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
};
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "FVP Base";
|
||||||
|
compatible = "arm,vfp-base", "arm,vexpress";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
chosen { };
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &v2m_serial0;
|
||||||
|
serial1 = &v2m_serial1;
|
||||||
|
serial2 = &v2m_serial2;
|
||||||
|
serial3 = &v2m_serial3;
|
||||||
|
};
|
||||||
|
|
||||||
|
psci {
|
||||||
|
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
|
||||||
|
method = "smc";
|
||||||
|
cpu_suspend = <0x84000001>;
|
||||||
|
cpu_off = <0x84000002>;
|
||||||
|
cpu_on = <0x84000003>;
|
||||||
|
sys_poweroff = <0x84000008>;
|
||||||
|
sys_reset = <0x84000009>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu-map {
|
||||||
|
cluster0 {
|
||||||
|
core0 {
|
||||||
|
cpu = <&CPU0>;
|
||||||
|
};
|
||||||
|
core1 {
|
||||||
|
cpu = <&CPU1>;
|
||||||
|
};
|
||||||
|
core2 {
|
||||||
|
cpu = <&CPU2>;
|
||||||
|
};
|
||||||
|
core3 {
|
||||||
|
cpu = <&CPU3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cluster1 {
|
||||||
|
core0 {
|
||||||
|
cpu = <&CPU4>;
|
||||||
|
};
|
||||||
|
core1 {
|
||||||
|
cpu = <&CPU5>;
|
||||||
|
};
|
||||||
|
core2 {
|
||||||
|
cpu = <&CPU6>;
|
||||||
|
};
|
||||||
|
core3 {
|
||||||
|
cpu = <&CPU7>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
idle-states {
|
||||||
|
entry-method = "arm,psci";
|
||||||
|
|
||||||
|
CPU_SLEEP_0: cpu-sleep-0 {
|
||||||
|
compatible = "arm,idle-state";
|
||||||
|
local-timer-stop;
|
||||||
|
arm,psci-suspend-param = <0x0010000>;
|
||||||
|
entry-latency-us = <40>;
|
||||||
|
exit-latency-us = <100>;
|
||||||
|
min-residency-us = <150>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
||||||
|
compatible = "arm,idle-state";
|
||||||
|
local-timer-stop;
|
||||||
|
arm,psci-suspend-param = <0x1010000>;
|
||||||
|
entry-latency-us = <500>;
|
||||||
|
exit-latency-us = <1000>;
|
||||||
|
min-residency-us = <2500>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU0:cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x0>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU1:cpu@1 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x1>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU2:cpu@2 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x2>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU3:cpu@3 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x3>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU4:cpu@100 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x100>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU5:cpu@101 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x101>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU6:cpu@102 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x102>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
CPU7:cpu@103 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "arm,armv8";
|
||||||
|
reg = <0x103>;
|
||||||
|
enable-method = "psci";
|
||||||
|
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
|
||||||
|
next-level-cache = <&L2_0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
L2_0: l2-cache0 {
|
||||||
|
compatible = "cache";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@80000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x00000000 0x80000000 0 0x7F000000>,
|
||||||
|
<0x00000008 0x80000000 0 0x80000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gic: interrupt-controller@2f000000 {
|
||||||
|
compatible = "arm,gic-v3";
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
interrupt-controller;
|
||||||
|
reg = <0x0 0x2f000000 0 0x10000>, // GICD
|
||||||
|
<0x0 0x2f100000 0 0x200000>, // GICR
|
||||||
|
<0x0 0x2c000000 0 0x2000>, // GICC
|
||||||
|
<0x0 0x2c010000 0 0x2000>, // GICH
|
||||||
|
<0x0 0x2c02f000 0 0x2000>; // GICV
|
||||||
|
interrupts = <1 9 4>;
|
||||||
|
|
||||||
|
its: its@2f020000 {
|
||||||
|
compatible = "arm,gic-v3-its";
|
||||||
|
msi-controller;
|
||||||
|
reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupts = <1 13 0xff01>,
|
||||||
|
<1 14 0xff01>,
|
||||||
|
<1 11 0xff01>,
|
||||||
|
<1 10 0xff01>;
|
||||||
|
clock-frequency = <100000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer@2a810000 {
|
||||||
|
compatible = "arm,armv7-timer-mem";
|
||||||
|
reg = <0x0 0x2a810000 0x0 0x10000>;
|
||||||
|
clock-frequency = <100000000>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
frame@2a830000 {
|
||||||
|
frame-number = <1>;
|
||||||
|
interrupts = <0 26 4>;
|
||||||
|
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pmu {
|
||||||
|
compatible = "arm,armv8-pmuv3";
|
||||||
|
interrupts = <0 60 4>,
|
||||||
|
<0 61 4>,
|
||||||
|
<0 62 4>,
|
||||||
|
<0 63 4>;
|
||||||
|
};
|
||||||
|
|
||||||
|
smb {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||||
|
<1 0 0 0x14000000 0x04000000>,
|
||||||
|
<2 0 0 0x18000000 0x04000000>,
|
||||||
|
<3 0 0 0x1c000000 0x04000000>,
|
||||||
|
<4 0 0 0x0c000000 0x04000000>,
|
||||||
|
<5 0 0 0x10000000 0x04000000>;
|
||||||
|
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-map-mask = <0 0 63>;
|
||||||
|
interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
|
||||||
|
<0 0 1 &gic 0 0 0 1 4>,
|
||||||
|
<0 0 2 &gic 0 0 0 2 4>,
|
||||||
|
<0 0 3 &gic 0 0 0 3 4>,
|
||||||
|
<0 0 4 &gic 0 0 0 4 4>,
|
||||||
|
<0 0 5 &gic 0 0 0 5 4>,
|
||||||
|
<0 0 6 &gic 0 0 0 6 4>,
|
||||||
|
<0 0 7 &gic 0 0 0 7 4>,
|
||||||
|
<0 0 8 &gic 0 0 0 8 4>,
|
||||||
|
<0 0 9 &gic 0 0 0 9 4>,
|
||||||
|
<0 0 10 &gic 0 0 0 10 4>,
|
||||||
|
<0 0 11 &gic 0 0 0 11 4>,
|
||||||
|
<0 0 12 &gic 0 0 0 12 4>,
|
||||||
|
<0 0 13 &gic 0 0 0 13 4>,
|
||||||
|
<0 0 14 &gic 0 0 0 14 4>,
|
||||||
|
<0 0 15 &gic 0 0 0 15 4>,
|
||||||
|
<0 0 16 &gic 0 0 0 16 4>,
|
||||||
|
<0 0 17 &gic 0 0 0 17 4>,
|
||||||
|
<0 0 18 &gic 0 0 0 18 4>,
|
||||||
|
<0 0 19 &gic 0 0 0 19 4>,
|
||||||
|
<0 0 20 &gic 0 0 0 20 4>,
|
||||||
|
<0 0 21 &gic 0 0 0 21 4>,
|
||||||
|
<0 0 22 &gic 0 0 0 22 4>,
|
||||||
|
<0 0 23 &gic 0 0 0 23 4>,
|
||||||
|
<0 0 24 &gic 0 0 0 24 4>,
|
||||||
|
<0 0 25 &gic 0 0 0 25 4>,
|
||||||
|
<0 0 26 &gic 0 0 0 26 4>,
|
||||||
|
<0 0 27 &gic 0 0 0 27 4>,
|
||||||
|
<0 0 28 &gic 0 0 0 28 4>,
|
||||||
|
<0 0 29 &gic 0 0 0 29 4>,
|
||||||
|
<0 0 30 &gic 0 0 0 30 4>,
|
||||||
|
<0 0 31 &gic 0 0 0 31 4>,
|
||||||
|
<0 0 32 &gic 0 0 0 32 4>,
|
||||||
|
<0 0 33 &gic 0 0 0 33 4>,
|
||||||
|
<0 0 34 &gic 0 0 0 34 4>,
|
||||||
|
<0 0 35 &gic 0 0 0 35 4>,
|
||||||
|
<0 0 36 &gic 0 0 0 36 4>,
|
||||||
|
<0 0 37 &gic 0 0 0 37 4>,
|
||||||
|
<0 0 38 &gic 0 0 0 38 4>,
|
||||||
|
<0 0 39 &gic 0 0 0 39 4>,
|
||||||
|
<0 0 40 &gic 0 0 0 40 4>,
|
||||||
|
<0 0 41 &gic 0 0 0 41 4>,
|
||||||
|
<0 0 42 &gic 0 0 0 42 4>;
|
||||||
|
|
||||||
|
/include/ "rtsm_ve-motherboard.dtsi"
|
||||||
|
};
|
||||||
|
|
||||||
|
panels {
|
||||||
|
panel@0 {
|
||||||
|
compatible = "panel";
|
||||||
|
mode = "XVGA";
|
||||||
|
refresh = <60>;
|
||||||
|
xres = <1024>;
|
||||||
|
yres = <768>;
|
||||||
|
pixclock = <15748>;
|
||||||
|
left_margin = <152>;
|
||||||
|
right_margin = <48>;
|
||||||
|
upper_margin = <23>;
|
||||||
|
lower_margin = <3>;
|
||||||
|
hsync_len = <104>;
|
||||||
|
vsync_len = <4>;
|
||||||
|
sync = <0>;
|
||||||
|
vmode = "FB_VMODE_NONINTERLACED";
|
||||||
|
tim2 = "TIM2_BCD", "TIM2_IPC";
|
||||||
|
cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
|
||||||
|
caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
|
||||||
|
bpp = <16>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
Loading…
Reference in New Issue